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101. 发明授权

US06606680B2 Method and apparatus for accessing banked embedded dynamic random access memory devices 有权
标题翻译：用于访问嵌入式嵌入式动态随机存取存储器件的方法和装置
公开(公告)号：US06606680B2
公开(公告)日：2003-08-12
申请号：US09895224
申请日：2001-06-29
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
IPC分类号： G06F1202
CPC分类号： G06F12/0897 , G11C7/22 , G11C11/408 , G11C2207/104
摘要： An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.
摘要翻译：公开了一种用于访问嵌入式动态随机存取存储器件的装置。用于访问堆叠式嵌入式动态随机存取存储器（DRAM）装置的装置包括通用功能控制逻辑和银行RAS控制器。一般的功能控制逻辑耦合到组合的嵌入式DRAM设备的每个组。耦合到一般功能控制逻辑，银行RAS控制器包括具有多个位的旋转移位寄存器。旋转移位寄存器内的每个位对应于组合嵌入式DRAM器件的每一组。这样，旋转移位寄存器的一位内的第一值允许访问分组的嵌入式DRAM设备的相关联的存储体，并且旋转移位寄存器的一位内的第二值拒绝对相关联的组的嵌入式DRAM 设备。

102. 发明授权

US06598086B1 Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer 失效
标题翻译：用于通过中间缓冲器控制从生产者到缓冲消费者的高频数字系统中的信息流的方法和系统
公开(公告)号：US06598086B1
公开(公告)日：2003-07-22
申请号：US09436961
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： H04L47/527 , H04L47/28 , H04L47/50 , H04L49/90
摘要： An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.
摘要翻译：信息处理系统包括多个依次连接的单元，包括第一单元，第二单元和第三单元。信息包从第一单元直接传输到第二单元，然后流向第三单元，并且多个单元中的每个单元提供指示该单元是否输出分组的相应的动态输出指示。所述信息处理系统还包括：控制单元，其确定利用所述多个动态输出指示中的所有多个单元的分组缓冲能力以及所述多个单元中的相邻单元之间的保证的分组流，如果所述第一单元可以输出一个数据包直接连到第二个单元没有丢包。响应于该确定，控制单元向第一单元输出控制信号。

103. 发明授权

US06574719B2 Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices 有权
标题翻译：用于与多个嵌入式动态随机存取存储器件同时通信的方法和装置
公开(公告)号：US06574719B2
公开(公告)日：2003-06-03
申请号：US09903720
申请日：2001-07-12
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F13/28 , G06F13/4243
摘要： An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.
摘要翻译：公开了一种用于在多个存储器件和处理器之间提供并发通信的装置。每个存储器件包括驱动器，相位/周期调整感测电路和总线对准通信逻辑。每个相位/周期调整感测电路检测来自存储器件内相应的驱动器的周期调整的发生。如果已经检测到循环调整的发生，则总线对准通信逻辑将处理器的循环调整的发生传达给处理器。总线对准通信逻辑还将循环调整的发生与其他存储器件中的总线对准通信逻辑进行通信。处理器内有多个接收器，并且每个接收器被设计成从存储器设备中的相应驱动器接收数据。每个接收器包括循环延迟块。接收到发生循环调整的接收器通知其他接收机没有接收周期调整的发生，以使用它们的周期延迟块来延迟输入数据至少一个周期。

104. 发明授权

US5809566A Automatic cache prefetch timing with dynamic trigger migration 失效
标题翻译：自动缓存预取定时与动态触发迁移
公开(公告)号：US5809566A
公开(公告)日：1998-09-15
申请号：US702407
申请日：1996-08-14
申请人： Mark Jay Charney , Pradeep Kumar Dubey , Thomas Robert Puzak , William John Starke
发明人： Mark Jay Charney , Pradeep Kumar Dubey , Thomas Robert Puzak , William John Starke
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3806 , G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F2212/6024 , G06F2212/6028
摘要： Dynamic migration of a cache prefetch request is performed. A prefetch candidate table maintains at least one prefetch candidate which may be executed as a prefetch request. The prefetch candidate includes one or more trigger addresses which correspond to locations in the instruction stream where the prefetch candidate is to be executed as a prefetch request. A jump history table maintains a record of target addresses of program branches which have been executed. The trigger addresses in the prefetch candidate are defined by the target addresses of recently executed program branches maintained in the jump history table. A pending prefetch table maintains a record of executed prefetch requests. When an operation such as a cache miss, cache hit, touch instruction or program branch is identified, the pending prefetch table is scanned to determine whether a prefetch request has been executed. If a prefetch request has been executed, the prefetch candidate which was used to execute that prefetch request is updated. That is, a new trigger address in the prefetch candidate is selected in order to reduce access latency.
摘要翻译：执行缓存预取请求的动态迁移。预取候选表维持至少一个可以作为预取请求执行的预取候选。预取候选包括一个或多个触发地址，其对应于将作为预取请求执行预取候选的指令流中的位置。跳转历史记录表维护已执行的程序分支的目标地址记录。预取候选中的触发地址由保持在跳转历史表中的最近执行的程序分支的目标地址定义。待处理的预取表维护执行的预取请求的记录。当识别诸如高速缓存未命中，缓存命中，触摸指令或程序分支的操作时，扫描挂起的预取表以确定是否已经执行了预取请求。如果已经执行了预取请求，则更新用于执行该预取请求的预取候选。也就是说，选择预取候选中的新的触发地址以便减少访问延迟。

105. 发明授权

US07913123B2 Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效
标题翻译：在跟踪过程和使用可编程可变数量的共享内存写入缓冲区的非跟踪过程之间同时共享内存控制器
公开(公告)号：US07913123B2
公开(公告)日：2011-03-22
申请号：US12210005
申请日：2008-09-12
申请人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
发明人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译：公开了一种装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。硬件跟踪设备捕获处理器中的硬件跟踪数据。硬件跟踪工具包含在处理器内。使用系统总线将硬件跟踪数据传输到系统存储器。系统内存包含在系统中。当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。系统内存的一部分用于存储跟踪数据。系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

106. 发明授权

US06604145B1 Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path 失效
标题翻译：用于通过中间缓冲器和共享数据路径来控制从生产者到缓冲用户的高频数字系统中的信息流的方法和系统
公开(公告)号：US06604145B1
公开(公告)日：2003-08-05
申请号：US09436963
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： H04L47/10 , H04L47/27 , H04L47/39
摘要： An information handling system includes a plurality of producers that output packets of information, at least one consumer of the packets, and an information pipeline coupling the consumer and at least a particular producer among the plurality of producers. The information pipeline includes a shared resource having a bandwidth shared by multiple of the plurality of producers. The information handling system further includes a control unit that regulates packet output of the particular producer and that receives as inputs a producer output indication indicating that the particular producer output a packet and a shared resource input indication indicating that a packet output by the particular producer has been accepted by the shared resource for transmission to the consumer. Based upon these inputs, a number of grant messages output to the particular producer within a feedback latency of the control unit, and a portion of the bandwidth allocated to the particular producer, the control unit whether the particular producer can output a packet without packet loss. In response to a determination that the particular producer can output a packet without packet loss, the control unit outputs a grant message to the particular producer indicating that the particular producer is permitted to output a packet.
摘要翻译：信息处理系统包括输出信息分组的多个生成器，分组的至少一个消费者，以及耦合消费者和多个生产者中的至少特定生产者的信息流水线。信息流水线包括具有由多个生产者中的多个共享的带宽的共享资源。信息处理系统还包括控制单元，其调节特定生产者的分组输出并且接收指示特定生成者输出分组的生成器输出指示和指示由特定生产者输出的分组的共享资源输入指示由共享资源接受传输给消费者。基于这些输入，在控制单元的反馈等待时间内向特定生产者输出的许多授权消息以及分配给特定生产者的带宽的一部分，控制单元特定生产者是否可以输出分组而不丢包。响应于确定特定制作者可以输出没有分组丢失的分组，控制单元向特定制作者输出指示特定制作者被允许输出分组的授权消息。

107. 发明授权

US06601105B1 Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system 有权
标题翻译：用于控制高频数字系统中的生产者和多个缓冲器之间的信息流的方法和系统
公开(公告)号：US06601105B1
公开(公告)日：2003-07-29
申请号：US09436960
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： G06F15/17
摘要： An information handling system includes a producer that outputs packets of information, a plurality of buffers that can each receive packets from the producer and output the packets, and a control unit. The control unit receives at least one producer output indication indicating whether the producer output a packet to one of the plurality of buffers and a plurality of buffer output indications that each indicate whether a respective one of the plurality of buffers has output a packet. Based upon capacities of the plurality of buffers, the producer output indications, the buffer output indications and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. If so, the control unit provides a grant message to the producer indicating that the producer is permitted to output a packet.
摘要翻译：信息处理系统包括输出信息包的生成器，可以从生产者接收分组并输出分组的多个缓冲器，以及控制单元。所述控制单元接收至少一个生成器输出指示，所述至少一个生成器输出指示指示所述生成器是否向多个缓冲器之一输出分组，以及多个缓冲器输出指示，每个指示所述多个缓冲器中的相应一个是否已经输出分组。基于多个缓冲器的能力，生成器输出指示，缓冲器输出指示和在控制单元的反馈等待时间内向生成器输出的许多准许消息，控制单元是否可以输出分组而不丢包。如果是，则控制单元向生产者提供指示允许生产者输出分组的授权消息。

108. 发明授权

US6075937A Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation 失效
公开(公告)号：US6075937A
公开(公告)日：2000-06-13
申请号：US40671
申请日：1998-03-18
申请人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
发明人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
IPC分类号： G06F9/455
CPC分类号： G06F9/455
摘要： Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

109. 发明授权

US5878208A Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring 失效
标题翻译：使用有限输出引脚和总线监控的指令轨迹重建方法和系统
公开(公告)号：US5878208A
公开(公告)日：1999-03-02
申请号：US758197
申请日：1996-11-25
申请人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon
发明人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/00
CPC分类号： G06F11/3466 , G06F11/349
摘要： Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. An internal performance monitor within the processor system is utilized to detect each occurrence of the execution of a specified number of instructions and each occurrence of the execution of a specified number of some specific type of instruction such as load instructions or store instructions and generate an output in response to each such occurrence. This information, in addition to each detected occurrence of an external interrupt, is then utilized in combination with the monitored bus traffic to reconstruct an instruction trace utilizing a limited number of output pins.
摘要翻译：处理器系统和内存子系统的性能预测对于正确了解系统内的工作负载非常重要。通常使用指令轨迹来确定指令的分配，寄存器依赖性的识别，分支路径分析和定时。如果已知初始架构状态，则可以通过监视总线流量来确定跟踪中的地址跟踪，数据地址和数据，来完成重建指令轨迹的一种众所周知的技术。如果可以获得关于实际指令序列的更确定的信息，则可以显着地减少从监视的总线业务重建指令轨迹的困难。处理器系统内的内部性能监视器被用于检测指定数量的指令的执行的每次出现，以及执行指定数量的某些特定类型的指令（例如加载指令或存储指令）并且产生输出响应于每个这样的事件。然后，除了每个检测到的外部中断的发生之外，还将该信息与被监视的总线业务结合使用，以利用有限数量的输出引脚来重构指令轨迹。

110. 发明授权

US5862371A Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring 失效
标题翻译：使用性能监视器输出和总线监控的指令轨迹重建方法和系统
公开(公告)号：US5862371A
公开(公告)日：1999-01-19
申请号：US758198
申请日：1996-11-25
申请人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon , Jack Chris Randolph
发明人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon , Jack Chris Randolph
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/349 , G06F2201/885
摘要： A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. To this end, an internal performance monitor within the processor system is utilized to generate an output each processor clock cycle which is indicative of the exact number of instructions which were executed during that clock cycle, an indication of whether or not a branch instruction was taken or not taken, an offset for each interrupt vector which has been taken, the number of data cache misses, the number of instruction cache misses, the number of store conditional instructions which were executed and the number of store conditional instructions which failed. This information, in combination with monitored bus traffic may be utilized to efficiently and accurately reconstruct an instruction trace without adversely affecting performance of the system under test.
摘要翻译：一种使用性能监视器输出和总线监控的指令轨迹重建方法和系统。处理器系统和内存子系统的性能预测对于正确了解系统内的工作负载非常重要。通常使用指令轨迹来确定指令的分配，寄存器依赖性的识别，分支路径分析和定时。如果系统的初始架构状态已知，则可以通过监视总线流量来确定跟踪期间的指令地址，数据地址和数据，来实现重建指令轨迹的一种众所周知的技术。如果可以获得关于实际指令序列的更确定的信息，则可以显着地减少从监视的总线业务重建指令轨迹的困难。为此，使用处理器系统内的内部性能监视器来产生每个处理器时钟周期的输出，其指示在该时钟周期期间执行的指令的精确数量，是否采用分支指令或不采取，已经采取的每个中断向量的偏移，数据高速缓存未命中的数量，指令高速缓存未命中的数量，被执行的存储条件指令的数量和存储条件指令的数量失败。可以将该信息与监视的总线业务相结合，以有效且准确地重建指令轨迹，而不会不利地影响被测系统的性能。

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