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101. 发明授权

US08399920B2 Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls 有权
标题翻译：半导体器件包括具有多个垂直取向侧壁的晶体管栅极
公开(公告)号：US08399920B2
公开(公告)日：2013-03-19
申请号：US11863535
申请日：2007-09-28
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76
CPC分类号： H01L29/4236 , H01L21/26586 , H01L29/42368 , H01L29/66621 , H01L29/66659 , H01L29/78 , H01L29/7834
摘要： A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.
摘要翻译：用于制造凹陷存取器晶体管栅极的方法具有增加的掩模未对准的容限。本发明的一个实施例包括在半导体晶片上形成垂直间隔层，然后蚀刻垂直间隔层和半导体晶片以在晶片中形成凹陷。然后在沟槽内和垂直间隔层上形成导电晶体管栅极层。蚀刻晶体管栅极层，暴露垂直间隔层。在蚀刻的导电栅极层上方并在垂直间隔层之上形成间隔层，然后间隔层和垂直间隔层被各向异性地蚀刻。在各向异性蚀刻垂直间隔层之后，垂直间隔层的一部分在垂直于半导体晶片的主表面的平面的方向插入在半导体晶片和蚀刻的导电晶体管栅极层之间。

102. 发明授权

US08384142B2 Non-planar thin fin transistor 有权
标题翻译：非平面薄鳍晶体管
公开(公告)号：US08384142B2
公开(公告)日：2013-02-26
申请号：US13193363
申请日：2011-07-28
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L21/00 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing.
摘要翻译：制造非平面晶体管的方法。翅片场效应晶体管（finFET）通常围绕翅片（例如，高，薄的半导体构件）构建。在制造过程中，翅片可能会遇到各种机械应力，例如在基体运动期间的惯性力和清洁步骤期间的流体力。如果翅片上的力太大，则翅片可能会断裂，并可能导致晶体管不起作用。在形成翅片的第二面之前支撑翅片的一侧在翅片结构中产生稳定性，从而抵消在制造过程中产生的许多机械应力。

103. 发明授权

US08372710B2 Vertical transistors 有权
标题翻译：垂直晶体管
公开(公告)号：US08372710B2
公开(公告)日：2013-02-12
申请号：US13329977
申请日：2011-12-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
摘要翻译：具有U形晶体管的半导体结构包括由衬底中的交叉沟槽限定的柱对的顶部的源/漏区域。一个支柱通过在周围的沟槽上方延伸的脊连接到一对中的另一个柱。柱的脊和下部在U形结构的相对侧限定U形通道，面对在那些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。还公开了形成半导体结构的方法。

104. 发明申请

US20130005102A1 Data Cells with Drivers and Methods of Making and Operating the Same 有权
公开(公告)号：US20130005102A1
公开(公告)日：2013-01-03
申请号：US13612361
申请日：2012-09-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： G11C11/40 , H01L27/105 , H01L27/10814 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

105. 发明授权

US08294511B2 Vertically stacked fin transistors and methods of fabricating and operating the same 有权
标题翻译：垂直堆叠鳍式晶体管及其制造和操作方法
公开(公告)号：US08294511B2
公开(公告)日：2012-10-23
申请号：US12950761
申请日：2010-11-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L25/00
CPC分类号： H01L21/823431 , H01L27/0886 , H01L27/10826 , H01L27/10879
摘要： A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.
摘要翻译：公开了一种在半导体鳍片中垂直堆叠（也称为垂直偏移）晶体管的半导体器件。半导体鳍片可以包括由第一沟槽分离并且在鳍片的第一掺杂区域中具有源极和漏极的下部晶体管。半导体鳍片还包括垂直偏离第一晶体管并由第二沟槽隔开的上晶体管，并且在鳍片的第二掺杂区域中具有源极和漏极。上和下堆叠栅极可以设置在翅片的侧壁上，使得下晶体管通过偏置下栅极而被激活，并且通过偏置上栅极来激活上晶体管。还公开了制造和操作该装置的方法。

106. 发明申请

US20120235214A1 LOCALLY 2 SIDED CHC DRAM ACCESS TRANSISTOR STRUCTURE 有权
标题翻译：本地2个CHC DRAM访问晶体管结构
公开(公告)号：US20120235214A1
公开(公告)日：2012-09-20
申请号：US13047774
申请日：2011-03-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10879 , H01L27/10826
摘要： A method for forming a DRAM memory with a two-sided transistor includes: providing a silicon finFET structure having at least two fins, and a trench between the fins; forming high ohmic gates on either side of the fins; forming a hole between each pair of high ohmic gates to enable connection between the pair of high ohmic gates; forming a gate on one side of the trench and underneath one of the pair of high ohmic gate; forming a layer of oxide over the gate; and depositing tungsten in the trench to form a thick layer of metal at the bottom to form a word line.
摘要翻译：用于形成具有双面晶体管的DRAM存储器的方法包括：提供具有至少两个散热片的硅finFET结构和鳍片之间的沟槽; 在翅片的两侧形成高欧姆门; 在每对高欧姆门之间形成一个孔，以使一对高欧姆门之间能够连接; 在沟槽的一侧形成栅极，并在该对高欧姆栅极之一的下面形成栅极; 在门上形成一层氧化物; 并且在沟槽中沉积钨以在底部形成厚的金属层以形成字线。

107. 发明授权

US08207583B2 Memory device comprising an array portion and a logic portion 有权
标题翻译：存储器件包括阵列部分和逻辑部分
公开(公告)号：US08207583B2
公开(公告)日：2012-06-26
申请号：US12940948
申请日：2010-11-05
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/70
CPC分类号： H01L27/108 , H01L21/0337 , H01L27/088 , H01L27/10876 , H01L27/10894
摘要： In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
摘要翻译：在本发明的实施例中，一种方法包括使用第一光刻掩模图案化半导体衬底的阵列部分中的第一多个半导体结构。该方法还包括使用第二光刻掩模在半导体衬底的逻辑部分上构图第二多个半导体结构。该方法还包括使用第二光刻掩模在第一多个半导体结构上图案化牺牲层。牺牲层与第二多个半导体结构同时被图案化。

108. 发明申请

US20120139039A1 Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls 有权
标题翻译：包括具有多个垂直定向的侧壁的晶体管门的半导体器件
公开(公告)号：US20120139039A1
公开(公告)日：2012-06-07
申请号：US13398491
申请日：2012-02-16
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L21/26586 , H01L29/42368 , H01L29/66621 , H01L29/66659 , H01L29/78 , H01L29/7834
摘要： A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.
摘要翻译：用于制造凹陷存取器晶体管栅极的方法具有增加的掩模未对准的容限。本发明的一个实施例包括在半导体晶片上形成垂直间隔层，然后蚀刻垂直间隔层和半导体晶片以在晶片中形成凹陷。然后在沟槽内和垂直间隔层上形成导电晶体管栅极层。蚀刻晶体管栅极层，暴露垂直间隔层。在蚀刻的导电栅极层上方并在垂直间隔层之上形成间隔层，然后间隔层和垂直间隔层被各向异性地蚀刻。在各向异性蚀刻垂直间隔层之后，垂直间隔层的一部分在垂直于半导体晶片的主表面的平面的方向插入在半导体晶片和蚀刻的导电晶体管栅极层之间。

109. 发明申请

US20120126885A1 DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME 有权
标题翻译：双环4F2 DRAM CHC电池及其制造方法
公开(公告)号：US20120126885A1
公开(公告)日：2012-05-24
申请号：US12950797
申请日：2010-11-19
申请人： Werner Juengling , Howard C. Kirsch
发明人： Werner Juengling , Howard C. Kirsch
IPC分类号： H01L29/78 , H03K17/00 , H01L21/28
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/66484 , H01L29/66787 , H01L29/7855
摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
摘要翻译：提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。还包括制造和操作设备的方法。一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

110. 发明申请

US20120104488A1 DATA CELLS AND CONNECTIONS TO DATA CELLS 有权
标题翻译：数据电池和连接数据电池
公开(公告)号：US20120104488A1
公开(公告)日：2012-05-03
申请号：US13323525
申请日：2011-12-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/78
CPC分类号： H01L27/105 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1052
摘要： Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion.
摘要翻译：公开了一种器件，其中包括晶体管和触点的器件。晶体管包括可以形成在相应支脚中的两个端子。触点包括垂直延伸的第一部分和相对于第一部分垂直延伸的第二部分。第二部分比第一部分宽。

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