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101. 发明申请

US20070263448A1 OPERATING METHOD OF A NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的操作方法
公开(公告)号：US20070263448A1
公开(公告)日：2007-11-15
申请号：US11778657
申请日：2007-07-17
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

102. 发明授权

US07291882B2 Programmable and erasable digital switch device and fabrication method and operating method thereof 有权
标题翻译：可编程和可擦除数字开关装置及其制造方法及其操作方法
公开(公告)号：US07291882B2
公开(公告)日：2007-11-06
申请号：US11162893
申请日：2005-09-27
申请人： Ching-Sung Yang , Wei-Zhe Wong
发明人： Ching-Sung Yang , Wei-Zhe Wong
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521
摘要： A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type memory transistor includes a first P-type doped region, a second P-type doped region, a second charge storage layer and a second control gate. A common bit line doped region is formed between the N-type memory transistor and the P type memory transistor and electrically connects the first N-type region to the second P-type doped region. A word line electrically connects the first control gate to the second control gate.
摘要翻译：提供可编程和可擦除的数字开关装置。在衬底上形成N型存储晶体管和P型存储晶体管。 N型存储晶体管包括第一N型掺杂区，第二N型掺杂区，第一电荷存储层和第一控制栅极。 P型存储晶体管包括第一P型掺杂区，第二P型掺杂区，第二电荷存储层和第二控制栅极。在N型存储晶体管和P型存储晶体管之间形成公共位线掺杂区域，并将第一N型区域电连接到第二P型掺杂区域。字线将第一控制栅极电连接到第二控制栅极。

103. 发明申请

US20060039200A1 NON-VOLATILE MEMORY CELL, FABRICATION METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非挥发性记忆体，制造方法及其操作方法
公开(公告)号：US20060039200A1
公开(公告)日：2006-02-23
申请号：US10907031
申请日：2005-03-17
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A non-volatile memory including a plurality of memory units is provided. Each of the memory units includes a first memory cell and a second memory cell. The first memory cell is disposed over the substrate. The second memory cell is disposed next to the sidewall of the first memory cell and over the substrate. The first memory cell includes a first gate disposed over the substrate, a first composite dielectric layer disposed between the first gate and the substrate. The second memory cell includes a second gate disposed over the substrate and a second composite dielectric layer disposed between the second gate and the substrate and between the second gate and the first memory cell. Each of the first and second composite dielectric layers includes a bottom dielectric layer, a charge-trapping layer and a top dielectric layer.
摘要翻译：提供包括多个存储单元的非易失性存储器。每个存储单元包括第一存储单元和第二存储单元。第一存储单元设置在衬底上。第二存储单元设置在第一存储单元的侧壁旁边且在衬底上。第一存储单元包括设置在衬底上的第一栅极，设置在第一栅极和衬底之间的第一复合介电层。第二存储单元包括设置在衬底上的第二栅极和设置在第二栅极和衬底之间以及第二栅极和第一存储单元之间的第二复合电介质层。第一和第二复合电介质层中的每一个包括底部电介质层，电荷俘获层和顶部电介质层。

104. 发明授权

US06898126B1 Method of programming a flash memory through boosting a voltage level of a source line 失效
标题翻译：通过提高源极线的电压来对闪存进行编程的方法
公开(公告)号：US06898126B1
公开(公告)日：2005-05-24
申请号：US10707440
申请日：2003-12-15
申请人： Ching-Sung Yang , Hsiang-Chung Chang , Wei-Zhe Wong
发明人： Ching-Sung Yang , Hsiang-Chung Chang , Wei-Zhe Wong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C5/145 , G11C16/10
摘要： A method of programming a flash memory through boosting a voltage level of a source line. The flash memory has n memory cell transistors cascaded in series, a local bit line positioned above the n memory cell transistors, a buried bit line positioned under the n memory cell transistors, and a source line positioned under the buried bit line. The method includes inputting a word line voltage to a control gate of a kth memory cell transistor, and after floating the local bit line, inputting a source line voltage to the source line for inducing an FN tunneling effect inside the kth memory cell transistor through capacitance coupling between the buried bit line and the source line.
摘要翻译：一种通过提高源极线的电压来编程闪速存储器的方法。闪速存储器具有串联级联的n个存储单元晶体管，位于n个存储单元晶体管上方的局部位线，位于n个存储单元晶体管下方的掩埋位线以及位于掩埋位线下方的源极线。该方法包括：将字线电压输入到存储单元晶体管的控制栅极，并且在浮置局部位线之后，向源极线输入源极线电压以引起内部的FN隧道效应存储单元晶体管，通过掩埋位线和源极线之间的电容耦合。

105. 发明授权

US06888190B2 EEPROM with source line voltage stabilization mechanism 失效
标题翻译： EEPROM具有源极线电压稳定机制
公开(公告)号：US06888190B2
公开(公告)日：2005-05-03
申请号：US10707080
申请日：2003-11-20
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/76 , H01L29/78
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/7883
摘要： A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep ion well. A shallow P well serving as a buried bit line is doped within the cell ion well. The shallow P well is isolated by an STI layer, wherein the STI layer has a thickness greater than a well depth of the shallow ion well. At least one memory transistor with a stacked gate, a source, and a drain is formed on the shallow ion well. The source of the memory transistor is electrically coupled to the cell N well to induce a capacitor between the cell N well and the deep P well during a read operation, thereby avoiding read current bounce or potential power crash. A bit line overlies the memory transistor and is electrically connected to the drain of the memory transistor via a bit line contact plug short-circuiting the drain of the memory transistor and the shallow P well.
摘要翻译：低压非易失性存储器阵列包括具有存储区域的N型半导体衬底。在半导体衬底中形成深P阱。电池N阱位于半导体衬底的存储区内。细胞N阱位于深离子阱的上方。作为掩埋位线的浅P阱掺杂在细胞离子阱内。浅P阱由STI层隔离，其中STI层的厚度大于浅离子阱的阱深度。在浅离子阱上形成至少一个具有堆叠栅极，源极和漏极的存储晶体管。存储晶体管的源极电耦合到电池N，以在读取操作期间在电池N阱和深P阱之间感应电容器，从而避免读取电流反弹或潜在功率崩溃。位线覆盖存储晶体管，并通过位线接触插头将存储晶体管的漏极电连接到短路存储晶体管的漏极和浅P阱。

106. 发明申请

US20050030789A1 METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS 有权
标题翻译：用于操作由P型存储器单元组成的NAND阵列存储器模块的方法
公开(公告)号：US20050030789A1
公开(公告)日：2005-02-10
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

107. 发明授权

US06717206B2 Structure of an embedded channel write/erase flash memory cell and fabricating method thereof 失效
标题翻译：嵌入式通道写入/擦除闪存单元的结构及其制造方法
公开(公告)号：US06717206B2
公开(公告)日：2004-04-06
申请号：US10064409
申请日：2002-07-11
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
摘要翻译：本发明涉及嵌入式通道写入/擦除闪存单元的结构及其制造方法，更具体地说，涉及组合CMOS器件和闪存单元的结构，其中闪存单元结构和CMOS器件同时制造在一种降低成本并简化工艺流程的基板。此外，保留能够执行高电压和低电压操作的CMOS器件。因此，本发明不仅可以有效提高闪存单元和CMOS器件的工作效率，而且其整体体积也小于通过组合分别设计和制造的CMOS器件和闪存单元获得的整体体积。

108. 发明授权

US06654284B2 Channel write/erase flash memory cell and its manufacturing method 失效
公开(公告)号：US06654284B2
公开(公告)日：2003-11-25
申请号：US10064365
申请日：2002-07-07
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： G11C1604
CPC分类号： H01L29/66825 , G11C14/00 , G11C16/0433 , H01L29/7881
摘要： A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.

109. 发明授权

US06501685B2 Channel write/erase flash memory cell and its manufacturing method 失效
标题翻译：通道写/擦除闪存单元及其制造方法
公开(公告)号：US06501685B2
公开(公告)日：2002-12-31
申请号：US09683580
申请日：2002-01-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： G11C1604
CPC分类号： H01L29/66825 , G11C14/00 , G11C16/0433 , H01L29/7881
摘要： A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.
摘要翻译：公开了一种能够执行该操作方法的伪动态操作方法和闪存单元。在闪存存储器的漏极端子附近的寄生电容器在操作期间可以在几微秒内被充电。通过使用在浮置栅极和源极之间的界面处较厚的第一氧化物层和在堆叠栅极下方的中心附近较薄的第一氧化物层来避免在浮动栅极和源极之间产生的干扰。

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