专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明申请

US20090086522A1 ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME 有权
标题翻译：地线接线结构和印刷线路板
公开(公告)号：US20090086522A1
公开(公告)日：2009-04-02
申请号：US12239900
申请日：2008-09-29
申请人： Atsushi HIRAISHI , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi HIRAISHI , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C5/06 , H05K1/18 , H05K7/00
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

102. 发明授权

US07478287B2 Semiconductor integrated circuit and electronic device 失效
标题翻译：半导体集成电路和电子设备
公开(公告)号：US07478287B2
公开(公告)日：2009-01-13
申请号：US11270608
申请日：2005-11-10
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11B20/20 , G01R31/28 , G01R31/26
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
摘要翻译：虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且由测量电路获得的延迟时间用于确定输出电路的信号转换时间。信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。以这种方式，实现了由最近端的反射点减轻反射的信号传输。

103. 发明申请

US20080290495A1 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US20080290495A1
公开(公告)日：2008-11-27
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/528
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

104. 发明申请

US20080266031A1 SEMICONDUCTOR DEVICE AND WIRING PART THEREOF 有权
标题翻译：半导体器件及其接线部分
公开(公告)号：US20080266031A1
公开(公告)日：2008-10-30
申请号：US12060941
申请日：2008-04-02
申请人： Yutaka UEMATSU , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
发明人： Yutaka UEMATSU , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
IPC分类号： H01P1/00
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/111 , H05K2201/0175 , H05K2201/0179 , H05K2201/09763 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H01L2924/00
摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.
摘要翻译：提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。

105. 发明授权

US07187069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07187069B2
公开(公告)日：2007-03-06
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

106. 发明申请

US20070047354A1 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US20070047354A1
公开(公告)日：2007-03-01
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

107. 发明授权

US07095661B2 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 有权
标题翻译：半导体存储器模块，存储器系统，电路，半导体器件和DIMM
公开(公告)号：US07095661B2
公开(公告)日：2006-08-22
申请号：US11019274
申请日：2004-12-23
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： G11C99/00
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50012
摘要： There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.
摘要翻译：存在的问题是，由于DIMM中的C / A信号通过DIMM中的寄存器分配到相应的DRAM，DQ信号直接从DIMM中的端子连接，因此它们的时序难以同步。提供用于加速高速运行的DIMM的C / A信号的寄存器，寄存器的布线设置为菊花链布线。然后，通过设置在DRAM中的定时调整电路，根据DRAM的位置而不同的C / A信号和时钟信号之间的布线延迟时间差使得从寄存器的延迟时间之和并且由于定时调整电路引起的延迟量等于最远的DRAM的延迟时间。

108. 发明授权

US06937494B2 Memory module, memory chip, and memory system 失效
公开(公告)号：US06937494B2
公开(公告)日：2005-08-30
申请号：US10699628
申请日：2003-10-31
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/16 , G11C5/00 , G11C5/06 , G11C11/401
CPC分类号： G11C5/063
摘要： A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.

109. 发明申请

US20050105318A1 Memory module, memory chip, and memory system 失效
标题翻译：内存模块，内存芯片和内存系统
公开(公告)号：US20050105318A1
公开(公告)日：2005-05-19
申请号：US10699628
申请日：2003-10-31
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/16 , G11C5/00 , G11C5/06 , G11C11/401
CPC分类号： G11C5/063
摘要： A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.
摘要翻译：存储器模块包括至少一个CAR和多个DRAM，其设置成在模块基板的一个面和另一个面上彼此靠近并相邻。 DRAM被分成多个存储器组。这些存储器组彼此相邻的存储器组彼此配对。这对之一是1排列的内存组，另一个是2排的内存组。这对存储器组通过具有短截线的T形支路结构的短路连接到CAR。信号接收侧的一对存储器组之一用作开放端。有源终端由信号非接收侧的一对存储器组中的另一个的终端电阻执行。随后，可以减少信号反射。

110. 发明授权

US06862246B2 Semiconductor apparatus which prevents generating noise and being influenced by noise 有权
标题翻译：防止产生噪声并受噪声影响的半导体装置
公开(公告)号：US06862246B2
公开(公告)日：2005-03-01
申请号：US10454404
申请日：2003-06-04
申请人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
发明人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
IPC分类号： G06F1/12 , G11C7/10 , G11C7/22 , G11C11/407 , H01L21/822 , H01L27/04 , H03K3/03 , H03K5/00 , H03L7/00 , H03L7/089 , H03L7/091 , H03L7/099 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , H03K3/0322 , H03K2005/00078 , H03K2005/00208 , H03L7/0895 , H03L7/091 , H03L7/0995
摘要： The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.
摘要翻译：本发明提供一种包括内部时钟生成单元和数据存储单元的半导体装置。内部时钟发生单元基于外部时钟信号和时钟控制信号产生内部时钟信号。数据存储单元，其基于内部时钟信号进行数据处理。内部时钟发生单元执行同步控制，使得内部时钟信号与外部时钟信号同步。数据存储单元基于数据处理生成时钟控制信号，并将时钟控制信号输出到内部时钟发生单元，以控制同步控制。数据存储单元可以控制内部时钟生成单元，使得在数据处理是数据读取处理的同时控制暂时中止或暂时抑制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式