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101. 发明授权

US06772315B1 Translation lookaside buffer extended to provide physical and main-memory addresses 失效
标题翻译：翻译后备缓冲区扩展为提供物理和主内存地址
公开(公告)号：US06772315B1
公开(公告)日：2004-08-03
申请号：US09867002
申请日：2001-05-24
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F1202
CPC分类号： G06F12/1027 , G06F12/06
摘要： A processor includes a translation look-aside buffer (TLB) that relates virtual page addresses to both physical page addresses and main-memory addresses. If the processor references a virtual page address in the TLB for which there is no corresponding information in cache, the processor passes the main-memory address directly to main memory, avoiding the latency normally associated with systems that translate a physical page address to a main-memory address before accessing information from main memory.
摘要翻译：处理器包括将虚拟页面地址与物理页面地址和主存储器地址相关联的翻译后备缓冲器（TLB）。如果处理器引用高速缓存中没有对应信息的TLB中的虚拟页面地址，则处理器将主存储器地址直接传递到主存储器，避免了与将物理页地址转换为主 - 从主内存访问信息之前的内存地址。

102. 发明申请

US20120182821A1 MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION 有权
标题翻译：支持错误检测和校正的记忆系统组件
公开(公告)号：US20120182821A1
公开(公告)日：2012-07-19
申请号：US13326590
申请日：2011-12-15
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/00 , G06F11/1016 , G06F11/1048 , G11C2029/0411
摘要： A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.
摘要翻译：一种包括存储器件和存储体的存储器系统。在操作期间，存储器装置接收同时访问存储器组的第一存储区域中的第一行的数据字的请求以及与存储器组的第二存储区域中的第二行与数据相关联的错误信息。存储器请求包括标识第一行的第一行地址和标识第二行的第二行地址。接下来，存储器件分别将第一行地址和第二行地址路由到存储体中的第一行解码器和第二行解码器。最后，存储装置使用第一行解码器对第一行地址进行解码以访问第一行，同时使用第二行解码器解码第二行地址以访问第二行。

103. 发明申请

US20100281289A1 Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits 审中-公开
标题翻译：具有毛刺允许位片电路的双向存储器接口
公开(公告)号：US20100281289A1
公开(公告)日：2010-11-04
申请号：US12743075
申请日：2008-11-14
申请人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
发明人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
IPC分类号： G06F1/12 , G06F1/04 , H03L7/06 , H03H7/01 , G06G7/12
CPC分类号： G06F13/1689
摘要： A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.
摘要翻译：描述了具有发送和接收操作模式的位分片电路。所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。

104. 发明申请

US20100235554A1 RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE 审中-公开
标题翻译：可重新点对点存储器接口
公开(公告)号：US20100235554A1
公开(公告)日：2010-09-16
申请号：US12679461
申请日：2008-09-05
申请人： Kun Yung Chang , Richard E. Perego , Fariborz Assaderaghi
发明人： Kun Yung Chang , Richard E. Perego , Fariborz Assaderaghi
IPC分类号： G06F13/14
CPC分类号： G06F13/385
摘要： Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting.
摘要翻译：描述装置的实施例。该装置中的接口电路在总线上接收或发送数字信号，并且被配置为根据存储在寄存器中的模式设置交替地操作数据总线接口电路或控制总线接口电路。例如，接口电路可以被预先配置为根据存储的模式设置将外部总线的线路解释为数据线或控制线。此外，存储模式设置可以在接口电路的操作期间被动态配置（例如，重新编程），使得随后的数字信号随后根据新的模式设置进行处理。

105. 发明申请

US20100128542A1 Reference Clock and Command Word Alignment 有权
标题翻译：参考时钟和命令字对齐
公开(公告)号：US20100128542A1
公开(公告)日：2010-05-27
申请号：US12598068
申请日：2008-05-08
申请人： Jade M. Kizer , Richard E. Perego
发明人： Jade M. Kizer , Richard E. Perego
IPC分类号： G11C7/22 , H03M9/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0891 , H03L7/18
摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.
摘要翻译：存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控制器。参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入命令信号进行采样的命令恢复时钟信号。存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

106. 发明申请

US20090319719A1 System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices 审中-公开
标题翻译：具有控制器装置，缓冲器装置和多种存储器件的系统
公开(公告)号：US20090319719A1
公开(公告)日：2009-12-24
申请号：US12411003
申请日：2009-03-25
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/06
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译：一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。第一多个信号线耦合到控制器设备。第二多个信号线耦合到第一存储器件和集成电路缓冲器件。第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。第三组信号线耦合到第一存储器件和集成电路缓冲器件。第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。第一信号线耦合到第一存储器件和集成电路缓冲器件。第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。

107. 发明申请

US20080209141A1 Memory System And Device With Serialized Data Transfer 有权
标题翻译：具有序列化数据传输的存储器系统和器件
公开(公告)号：US20080209141A1
公开(公告)日：2008-08-28
申请号：US12116439
申请日：2008-05-07
申请人： Richard E. Perego , Fredrick A. Ware
发明人： Richard E. Perego , Fredrick A. Ware
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
摘要翻译：具有序列化数据传输的存储系统。存储器系统包括在存储器控制器和多个存储器件内。存储器控制器从主机接收多个写入数据值，并将写入数据值作为相应串行比特流输出。每个存储器件从存储器控制器接收至少一个串行比特流，并将串行比特流转换为一组并行比特以进行存储。

108. 发明授权

US07206896B2 Integrated circuit buffer device 失效
标题翻译：集成电路缓冲器
公开(公告)号：US07206896B2
公开(公告)日：2007-04-17
申请号：US11119031
申请日：2005-04-29
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion provides a first control signal to the first memory device. The first control signal specifies a read operation such that the first memory device provides a first data, accessed from a memory location based on the first address, to the integrated circuit buffer device in response to the first control signal specifying the read operation. A third interface portion provides a first clock signal to the first memory device. The first clock signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion receives the first data. A second interface includes a first interface portion to provide a second address to a second memory device. A second interface portion provides a second control signal to the second memory device. A third interface portion provides a second clock signal to the second memory device. A fourth interface portion receives the second data. A first transmitter circuit transmits the first read data and the second read data to the controller device.
摘要翻译：集成电路缓冲器件包括用于从控制器装置接收控制信息和地址信息的第一接收器电路。第一接口包括向第一存储器件提供第一地址的第一接口部分。第二接口部分向第一存储器件提供第一控制信号。第一控制信号指定读操作，使得第一存储器件响应于指定读操作的第一控制信号，将从第一地址的存储器位置访问的第一数据提供给集成电路缓冲器件。第三接口部分向第一存储器件提供第一时钟信号。第一时钟信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。第四接口部分接收第一数据。第二接口包括向第二存储器设备提供第二地址的第一接口部分。第二接口部分向第二存储器件提供第二控制信号。第三接口部分向第二存储器件提供第二时钟信号。第四接口部分接收第二数据。第一发送器电路将第一读取数据和第二读取数据发送到控制器装置。

109. 发明授权

US07051151B2 Integrated circuit buffer device 失效
标题翻译：集成电路缓冲器
公开(公告)号：US07051151B2
公开(公告)日：2006-05-23
申请号：US10272024
申请日：2002-10-15
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012 , Y02D10/14
摘要： An integrated circuit buffer device including a first port and a second port. The first port to receive data from a first integrated circuit memory device, and the second port to receive data from a second integrated circuit memory device. The integrated circuit buffer device further includes a multiplexer to output a data stream that includes the data received from the first integrated circuit memory device and the data received from the second integrated circuit memory device. In addition, the integrated circuit buffer device includes an interface including transmit circuitry to transmit the data stream to an integrated circuit controller device.
摘要翻译：一种包括第一端口和第二端口的集成电路缓冲器件。从第一集成电路存储器件接收数据的第一端口，以及用于从第二集成电路存储器件接收数据的第二端口。集成电路缓冲装置还包括多路复用器，用于输出包括从第一集成电路存储器件接收的数据和从第二集成电路存储器件接收的数据的数据流。此外，集成电路缓冲器件包括包括用于将数据流传输到集成电路控制器设备的发送电路的接口。

110. 发明授权

US07017002B2 System featuring a master device, a buffer device and a plurality of integrated circuit memory devices 失效
标题翻译：具有主设备，缓冲设备和多个集成电路存储设备的系统
公开(公告)号：US07017002B2
公开(公告)日：2006-03-21
申请号：US10952610
申请日：2004-09-28
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
摘要翻译：存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。存储器子系统包括耦合到多个存储器件的缓冲器件。可以通过专用点对点链路和对应的存储器子系统升级存储器系统。主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信。

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