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101. 发明授权

US5793087A Segmented non-volatile memory array having multiple sources 失效
公开(公告)号：US5793087A
公开(公告)日：1998-08-11
申请号：US814326
申请日：1997-03-11
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/04 , H01L27/115 , H01L29/78
CPC分类号： H01L27/11519 , G11C16/0416 , H01L27/115
摘要： An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns. The metallic source line of one of the erase blocks extends over, but is not connected to, the adjacent erase block, with the source lines of the erase blocks preferably being connected to a common source line decoder used to control the status of a selected one of the source lines so that a selected one of the erase blocks can be erased.

102. 发明授权

US5781477A Flash memory system having fast erase operation 失效
公开(公告)号：US5781477A
公开(公告)日：1998-07-14
申请号：US604815
申请日：1996-02-23
申请人： Darrell D. Rinerson , Roger R. Lee , Christophe J. Chevallier
发明人： Darrell D. Rinerson , Roger R. Lee , Christophe J. Chevallier
IPC分类号： G11C5/14 , G11C16/16 , G11C16/30 , G11C7/00
CPC分类号： G11C16/16 , G11C16/30 , G11C5/145
摘要： A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased. The positive voltage is greater in magnitude than the external primary voltage source and is preferably produced utilizing a charge pump circuit powered by the primary voltage source. The relatively large source voltage enables the cell to be erased rapidly and with a reduced tendency to produce positive charges which can be trapped in the gate oxide intermediate the floating gate and the channel/source of the cell.

103. 发明授权

US5771346A Apparatus and method for detecting over-programming condition in multistate memory device 失效
公开(公告)号：US5771346A
公开(公告)日：1998-06-23
申请号：US736195
申请日：1996-10-24
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F11/10 , G11C11/56 , G11C29/00 , G11C29/52 , G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C11/5621 , G11C11/5628 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/52 , G11C29/76 , G11C29/82 , G11C7/1039 , G11C16/04 , G11C2029/0409 , G11C2211/5643 , G11C29/00
摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

104. 发明授权

US5764568A Method for performing analog over-program and under-program detection for a multistate memory cell 失效
公开(公告)号：US5764568A
公开(公告)日：1998-06-09
申请号：US736568
申请日：1996-10-24
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C11/56 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3463 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5644 , G11C29/00
摘要： A method for detecting an under-programming or over-programming condition in a multistate memory cell. The method uses three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. Control circuitry is used which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell. This information is used by a controller to determine if a memory cell has been over-programmed, under-programmed, or properly programmed. If the cell has not been properly programmed, then additional programming pulses are applied (in the case of under-programming) or an error flag is set and the programming algorithm is terminated (in the case of an over-programmed cell).

105. 发明授权

US5751944A Non-volatile memory system having automatic cycling test function 失效
标题翻译：具有自动循环测试功能的非易失性存储器系统
公开(公告)号：US5751944A
公开(公告)日：1998-05-12
申请号：US508797
申请日：1995-07-28
申请人： Frankie F. Roohparvar , Christophe J. Chevallier
发明人： Frankie F. Roohparvar , Christophe J. Chevallier
IPC分类号： G11C29/46 , G11C29/52 , G01R31/28
CPC分类号： G11C29/52 , G11C29/46
摘要： A flash memory system having the capability of automatically executing consecutive program-erase cycles for the purpose of measuring the endurance of the memory. The memory system may be switched to a test mode which triggers the autocycling by applying a high voltage to two of the package pins of the system which normally are coupled to low voltage sources. The system includes an internal state machine which, in normal operation, is implemented to perform flash cell programming, erasing and reading, with the erasing sequence including a preprogram step where, prior to the erase, all cells are programmed. When placed in the autocycle mode by application of the high voltages to the pins, the state machine is caused to enter the erase sequence, including the preprogram step. Once the first erase sequence is concluded, circuitry is provided that causes the state machine to automatically initiate a further erase sequence. The erase sequences will continue until interrupted, with each sequence constituting a single program-erase cycle.
摘要翻译：具有能够自动执行连续编程擦除周期以便测量存储器的耐久性的闪速存储器系统。存储器系统可以切换到测试模式，其通过对通常耦合到低电压源的系统的两个封装引脚施加高电压来触发自动循环。该系统包括内部状态机，其在正常操作中被实现以执行闪存单元编程，擦除和读取，其中擦除顺序包括预编程步骤，其中在擦除之前，所有单元被编程。当通过对引脚施加高电压而置于自动循环模式时，使状态机进入擦除顺序，包括预编程步骤。一旦完成了第一个擦除顺序，就提供了使状态机自动启动进一步擦除顺序的电路。擦除序列将继续直到中断，每个序列构成单个编程擦除周期。

106. 发明申请

US20120099011A1 CMOS IMAGER WITH INTEGRATED CIRCUITRY 有权
标题翻译：具有集成电路的CMOS图像
公开(公告)号：US20120099011A1
公开(公告)日：2012-04-26
申请号：US13341512
申请日：2011-12-30
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/335
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。集成CMOS成像器和外围电路允许单片图像感测设备。

107. 发明申请

US20110228153A1 CMOS IMAGER WITH INTEGRATED CIRCUITRY 有权
标题翻译：具有集成电路的CMOS图像
公开(公告)号：US20110228153A1
公开(公告)日：2011-09-22
申请号：US13118066
申请日：2011-05-27
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/335
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。集成CMOS成像器和外围电路允许单片图像感测设备。

108. 发明申请

US20110188282A1 Memory architectures and techniques to enhance throughput for cross-point arrays 有权
标题翻译：内存架构和技术，以增强交叉点阵列的吞吐量
公开(公告)号：US20110188282A1
公开(公告)日：2011-08-04
申请号：US12658138
申请日：2010-02-02
申请人： Christophe J. Chevallier , Sri Namala , Chang Hua Siau , David Eggleston
发明人： Christophe J. Chevallier , Sri Namala , Chang Hua Siau , David Eggleston
IPC分类号： G11C5/02 , H01L21/8239 , G11C8/10
CPC分类号： H01L27/1052 , G11C5/025 , G11C5/04 , G11C5/063 , G11C5/066 , G11C8/10 , H01L27/0207 , H01L27/0688
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，其被配置为增强包括诸如基于第三维存储器技术的存储器元件的存储器元件的交叉点阵列的吞吐量。在至少一些实施例中，集成电路包括阵列，其包括在与基板平行的平面内的边界内的FEOL逻辑层上形成BEOL的阵列线和阵列线。此外，集成电路包括布置在逻辑层内的阵列线解码器，该阵列线路解码器位于与边界共同延伸并且在基板和阵列之间的区域内。在一些实施例中，在阵列之下的外围电路（例如阵列线解码器）的布置可以保持或优化用于吞吐量增强的管芯效率。

109. 发明授权

US07952631B2 CMOS imager with integrated circuitry 有权
标题翻译： CMOS成像器集成电路
公开(公告)号：US07952631B2
公开(公告)日：2011-05-31
申请号：US12533146
申请日：2009-07-31
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/225 , H04N5/76 , H04N3/14
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。集成CMOS成像器和外围电路允许单片图像感测设备。

110. 发明申请

US20090284623A1 CMOS IMAGER WITH INTEGRATED NON-VOLATILE MEMORY 有权
标题翻译：具有集成非易失性存储器的CMOS成像器
公开(公告)号：US20090284623A1
公开(公告)日：2009-11-19
申请号：US12533146
申请日：2009-07-31
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/76 , H04N5/335 , H04N5/225
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking light received by the CMOS imager. The protective layer can be a metal layer used as an interconnect over other areas of the substrate or an opaque layer provided during the fabrication process. Integrating a CMOS imager, non-volatile memory and peripheral circuitry for decoding and processing optical information received by the CMOS imager allows for a single chip image sensing device, such as a digital camera.
摘要翻译： CMOS成像器和非易失性存储器与逻辑和支持电路一起集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。保护层覆盖包含在基板上的用于阻挡由CMOS成像器接收的光的非易失性存储器。保护层可以是用作在基板的其它区域上的互连的金属层或在制造工艺期间提供的不透明层。集成CMOS成像器，用于解码和处理由CMOS成像器接收的光学信息的非易失性存储器和外围电路允许单片图像感测装置，例如数字照相机。

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