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91. 发明专利

JPS518309B1 失效
公开(公告)号：JPS518309B1
公开(公告)日：1976-03-16
申请号：JP2834369
申请日：1969-04-12
IPC分类号： H03K5/00 , H03K3/70 , H04B1/00 , H04L7/027

92. 实用新型

JPS518350Y2 失效
公开(公告)号：JPS518350Y2
公开(公告)日：1976-03-05
申请号：JP6472571
申请日：1971-07-23
IPC分类号： H03K3/02 , H03K3/03 , H03K3/64 , H03K3/66 , H03K3/70 , H03K3/86 , H03K5/13 , H03K5/14 , H03K5/153

93. 发明专利

JPS50120758A 失效
公开(公告)号：JPS50120758A
公开(公告)日：1975-09-22
申请号：JP2626374
申请日：1974-03-08
IPC分类号： H03K3/02 , H03K3/70 , H03K5/00

94. 发明专利

JPS5080066A 失效
公开(公告)号：JPS5080066A
公开(公告)日：1975-06-28
申请号：JP12749073
申请日：1973-11-12
IPC分类号： H03L7/10 , H03K3/70 , H03L7/107

95. 实用新型

JPS473551Y1 失效
公开(公告)号：JPS473551Y1
公开(公告)日：1972-02-07
申请号：JP11708566
申请日：1966-12-24
IPC分类号： H03K3/70 , G10K9/12 , H03K3/30

96. 发明授权

US12125674B2 Surface charge and power feedback and control using a switch mode bias system 有权
公开(公告)号：US12125674B2
公开(公告)日：2024-10-22
申请号：US16871613
申请日：2020-05-11
申请人： Advanced Energy Industries, Inc.
发明人： Daniel Carter
IPC分类号： H01J37/32 , H03K3/64 , H03K3/70 , H03K3/78
CPC分类号： H01J37/32137 , H01J37/32715 , H03K3/64 , H03K3/70 , H03K3/78 , H01J37/32183 , H01J2237/004 , H01J2237/334
摘要： Systems, methods and apparatus for regulating ion energies in a plasma chamber and avoiding excessive and damaging charge buildup on the substrate surface and within capacitive structures being built on the surface. An exemplary method includes placing a substrate in a plasma chamber, forming a plasma in the plasma chamber, controllably switching power to the substrate so as to apply a periodic voltage function (or a modified periodic voltage function) to the substrate, and modulating, over multiple cycles of the periodic voltage function, the periodic voltage function responsive to a defined distribution of energies of ions at the surface of the substrate so as to effectuate the defined distribution of ion energies on a time-averaged basis, and to maintain surface charge buildup below a threshold.

97. 发明授权

US09740234B1 On-chip clock controller 有权
公开(公告)号：US09740234B1
公开(公告)日：2017-08-22
申请号：US15087171
申请日：2016-03-31
申请人： QUALCOMM Incorporated
发明人： Hong Kim , Paul Policke , Anirudh Kadiyala
IPC分类号： G06F1/04 , G06F1/06 , H03K3/037 , G06F13/40 , H03K5/135 , H03K5/1252 , H03K3/70 , H03K3/356 , H03K17/284
CPC分类号： G06F1/06 , G06F1/04 , G06F13/4072 , H03K3/037 , H03K3/356052 , H03K3/70 , H03K5/1252 , H03K5/135 , H03K17/284
摘要： An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.

98. 发明授权

US07397291B1 Clock jitter minimization in a continuous time sigma delta analog-to-digital converter 有权
标题翻译：连续时间Σ-Δ模数转换器中的时钟抖动最小化
公开(公告)号：US07397291B1
公开(公告)日：2008-07-08
申请号：US11621844
申请日：2007-01-10
申请人： John J. Parkes, Jr. , James G. Mittel , James J. Riches
发明人： John J. Parkes, Jr. , James G. Mittel , James J. Riches
IPC分类号： H03K3/70 , H03K3/023 , H03M1/66
CPC分类号： H03M3/372 , H03M3/424
摘要： A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
摘要翻译：适用于连续时间Σ-Δ模数转换器中的反馈转换器的数 - 模转换器。数模转换器具有离散时间数字信号输入，接受与第一数据时钟信号和离散时钟发生器的断言同步的数字信号采样，该离散时钟发生器响应于接收到第一数据信号的断言而产生输出脉冲数据时钟。输出脉冲被断言固定持续时间，与第一个数据时钟的抖动无关。数模转换器还包括连续时间模拟输出，其在断言输出脉冲期间产生具有对应于数字信号采样的幅度的连续时间模拟输出信号。

99. 发明申请

US20050017779A1 Circuit for the temporary interruption of a sync signal 有权
标题翻译：用于暂时中断同步信号的电路
公开(公告)号：US20050017779A1
公开(公告)日：2005-01-27
申请号：US10857598
申请日：2004-05-27
申请人： Mauro Osvaldella
发明人： Mauro Osvaldella
IPC分类号： G06F1/08 , G06F1/10 , H03K3/70 , H03K5/1252 , H03K3/02
CPC分类号： G06F1/10 , G06F1/08 , H03K3/70 , H03K5/1252
摘要： A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.
摘要翻译：一种同步信号的停止和释放电路，用于暂时中止或中断同步信号，输入同步信号具有多个前沿和多个后沿，该电路包括接收输入同步信号并提供的第一分频器由从前沿开始的同步信号除以2的第一信号，接收反向输入同步信号并提供由从后沿开始分频2的同步信号构成的第二信号的第二分频器， OR电路，其接收第一信号和第二信号，并且提供输出同步信号，用于第一分频器和第二除法器的停止电路以及由停止电路产生的用于暂时中断输出同步信号的异步命令信号。

100. 发明授权

US5808486A Glitch free clock enable circuit 失效
标题翻译：无毛刺时钟使能电路
公开(公告)号：US5808486A
公开(公告)日：1998-09-15
申请号：US842104
申请日：1997-04-28
申请人： David Alan Smiley
发明人： David Alan Smiley
IPC分类号： G06F1/08 , G06F1/10 , H03K3/70 , H03K5/13 , H03K5/00
CPC分类号： H03K5/13 , G06F1/08 , G06F1/10 , H03K3/70
摘要： A clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate. The output of the AND gate is the output clock signal.
摘要翻译：一种时钟使能电路，其产生输出时钟信号，使得当使能输出信号变为逻辑假时，输出时钟信号以不产生毛刺的方式返回其稳态值，并且保持占空比输入时钟。电路包括正沿触发的第一D触发器，负沿触发的第二D触发器和双输入与门。第一个触发器将D输入连接到恒定的正电压，正边沿触发的时钟输入连接到输入时钟信号，Q输出连接到与门，并且Q补码输出连接到异步复位的第二个触发器。第二个触发器将D输入连接到使能输出信号，负沿触发时钟输入连接到输入时钟信号，Q输出连接到第一个触发器的异步复位和Q-补码输出连接到与门。与门的输出是输出时钟信号。

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