专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明专利

JPH02197910A LIGHT CALCULATOR 失效
公开(公告)号：JPH02197910A
公开(公告)日：1990-08-06
申请号：JP21081289
申请日：1989-08-17
申请人： BOEING CO
发明人： SHII DEIBITSUTO KIYATSUPUSU , AARU AARON FUOOKU
IPC分类号： G06E1/04 , G06E1/00 , G06E1/06
摘要： PURPOSE: To realize the extra-high speed processing by using the parallel remainder calculation method for logical operation or operation without carry and converting parallel remainders to binary numbers. CONSTITUTION: A register converter 60a converts all figures of a number to remainder expressions modulo 2, and a remainder converter 60b converts them to remainder expressions modulo 3, and a remainder converter 60c converts them to remainder expressions modulo 5. A remainder converter 52 has three separated remainder converters 70a to 70c correspondingly to radixes 2, 3, and 5. Remainder 2 converts converters 60a and 70a to present the outputs along output lines 62a and 72a, and remainder 3 converts 60b and 70b to present the outputs along output lines 62b and 72b, and remainder 5 converts converters 60c and 70c to present the outputs along output lines 62c and 72c. Thus, the extra-high speed processing is realized.

92. 发明专利

JPH02171905A OPTICAL ADDER 失效
公开(公告)号：JPH02171905A
公开(公告)日：1990-07-03
申请号：JP32874988
申请日：1988-12-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KUROKAWA TAKASHI , FUKUSHIMA SEIJI
IPC分类号： G06E1/04
摘要： PURPOSE:To attain a rapid processing by converting respective bits of two input data to be added into spatial optical patterns and simultaneously adding plural elements. CONSTITUTION:Liquid crystal panels LC1A, LC1B on which picture elements corresponding to respective bits of input data A, B are respectively arranged are irradiated with parallel beams outputted from respective semiconductor lasers LD1A, LD1B and optical patterns having liniear polarized state p/s corresponding to data 0/1 are outputted from respective picture elements. Data obtained by executing the EXOR operation between data SUM and carry data CBB are stored in a light writing type spatial light modulator(SLM)S and the result of NAND operation between the data SUM and a carry data CBB is stored in a SLMC and the final full added result SUM is inputted to an array sensor(AS), photoelectrically converted and read out. Since many elements can be simultaneously added in parallel, the adding time can be sharply reduced.

93. 发明专利

JPH01195452A OPTICAL ARITHMETIC UNIT 失效
公开(公告)号：JPH01195452A
公开(公告)日：1989-08-07
申请号：JP2059788
申请日：1988-01-29
申请人： NEC CORP
发明人： KAWAI SHIGERU , YOSHIHARA KAZUHIRO , KUBOTA KEIICHI , HIROSE YUTAKA
IPC分类号： G03F3/00 , G06E1/04 , H01S5/00
摘要： PURPOSE:To make arithmetic operation executable in parallel with each other at a high speed by using an optical arithmetic unit provided with the 1st-3rd optical arithmetic sections. CONSTITUTION:The input surface 11 of the initial stage is constituted of an array-like light source 1 composed of plural semiconductor lasers 1a which can be modulated at high speeds and are arranged in the form of an array and a lens array 2a in which micro-lenses are arrayed at the locations corresponding to each light emitting point of the light source 1. The light emitted from the light source 1 is collimated by the lens array 2a and deflected by a light branching element 3a constituted by hologram. The deflected light is made incident to a threshold element array composed of an optical bistable laser 4a and the threshold element at the part where the light from its own bit and the light from an adjacent higher-order bit meet each other outputs '1', namely, emits light. The other threshold element outputs '0' (does not emit light). The light thus deflected is made incident to a threshold element array 4c where the light is binary coded and, finally, answers are obtained in the transversal direction of each bit. Therefore, an optical arithmetic unit which can execute algorithm by multivalue expression in parallel at a high speed by using light is obtained.

94. 发明专利

JPH01195430A OPTICAL ARITHMETIC UNIT 失效
公开(公告)号：JPH01195430A
公开(公告)日：1989-08-07
申请号：JP2059688
申请日：1988-01-29
申请人： NEC CORP
发明人： KAWAI SHIGERU , YOSHIHARA KAZUHIRO , KUBOTA KEIICHI , HIROSE YUTAKA
IPC分类号： G02F3/00 , G06E1/04 , H01S5/00
摘要： PURPOSE:To make the speed of parallel subtraction faster by obtaining an answer in such a way that the threshold element at which the longitudinal direction and transversal direction of the light deflected by a light branching element intersect each other is caused to issue a signal and the light of the signal becomes the incident light of the light branching element of the next stage, and then, the answer is obtained at the threshold element of the final stage after performing calculation four times. CONSTITUTION:The light emitted from an array-like light source 1 is made incident to an output surface 4a after it is deflected by a light branching element 3a. The light emitted from an optical bistable laser 5 is made incident to a threshold element array 4b after it is collimated by a lens array 2a and deflected by a light branching element 3b. The light made incident to the array 4b is binary coded and made incident to a threshold element array 4c where it is binary coded after it is deflected by a light branching element 3c. The light emitted from the threshold element array 4c is deflected by a light branching element 3d and the deflected light is binary coded by threshold element array 4d. Final answers are obtained in the transversal direction of each bit. Therefore, algorithm of multivalue expression can be executed in parallel at a high speed by using light.

95. 发明专利

JPS60134383A PRODUCT AND SUM CALCULATOR USABLE FOR SOLUTION OF PLURAL AND SIMULTANEOUS DIFFERENTIAL EQUATIONS 失效
公开(公告)号：JPS60134383A
公开(公告)日：1985-07-17
申请号：JP24082383
申请日：1983-12-22
申请人： KUROKAWA KAZUO
发明人： KUROKAWA KAZUO
IPC分类号： G06G7/38 , G06E1/04 , G06F7/53 , G06F17/12 , G06F17/13 , G06F17/16 , G06G7/32 , G06J1/00
摘要： PURPOSE:To increase the calculation speed by using light emitting elements which are provided at every bit of condition variables and plural photodetectors which are provided in opposition to these emitting elements, and executing product and sum calculation of plural and simultaneous differential equations in parallel. CONSTITUTION:In a light emitting part 1 for setting and a photodetecting part 2 for setting, light of a light emitting diode L irradiates all photodetectors D on a chip when an input signal is impressed on the light emitting diode L. As for the photodetector D, the output voltage is amplified when corresponding emitting elements emit, and the output is supplied to a coefficient multiplication switch part 3. The emitting elements emit and the integrated photodiode in the photodetecting part 2 operates. Thus, switching of the coefficient multiplication switch part 3 is executed.

96. 发明专利

JP4265038B2 Image processing apparatus 有权
公开(公告)号：JP4265038B2
公开(公告)日：2009-05-20
申请号：JP21834999
申请日：1999-08-02
申请人：ソニー株式会社
发明人：真一吉村
IPC分类号： H04N5/33 , G06E1/04 , G06F7/00 , G06F7/38 , G06F15/00 , H01L27/00 , H01L27/146 , H04N5/335 , H04N5/369 , H04N5/3745 , H04N5/376 , H04N5/378
CPC分类号： H01L27/146

97. 发明专利

JP2536452B2 失效
公开(公告)号：JP2536452B2
公开(公告)日：1996-09-18
申请号：JP12407794
申请日：1994-06-06
申请人： NIPPON ELECTRIC CO
发明人： BAARIN HA , YAO RI
IPC分类号： G06E1/06 , G06E1/04 , G06E3/00 , G06F7/42 , G06F7/506 , G06F7/508 , G06F7/53 , G11C15/00
摘要： An opto-electronic shared content-addressable memory processor is used to perform parallel modified signed-digit (MSD) arithmetic operations. The MSD arithmetic operation (addition or subtraction of two N-bit numbers) is decomposed into a matrix-matrix multiplication followed by a combination of a threshold and logic operations.

98. 发明专利

JPH087641B2 失效
公开(公告)号：JPH087641B2
公开(公告)日：1996-01-29
申请号：JP19423387
申请日：1987-08-03
IPC分类号： G02F3/00 , G06E1/04 , G06F7/508

99. 发明专利

JPH087640B2 失效
公开(公告)号：JPH087640B2
公开(公告)日：1996-01-29
申请号：JP19423287
申请日：1987-08-03
IPC分类号： G02F3/00 , G06E1/04 , G06F7/508

100. 发明专利

JPH0561088A OPTICAL CODING METHOD AND OPTICAL COMPUTING METHOD AND OPTICAL COMPUTING ELEMENT 失效
公开(公告)号：JPH0561088A
公开(公告)日：1993-03-12
申请号：JP22186191
申请日：1991-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI HIDEO , NAGATSU AKITO
IPC分类号： G02F3/00 , G06E1/04 , G06F3/00 , G06G7/14
摘要： PURPOSE:To allow the execution of the algorithm by many-valued expression at a high speed in parallel in the state of light by expressing respective picture elements by vectors consisting of plural picture elements expressed by the presence or absence of light and spacially expressing the number based on the many values. CONSTITUTION:The respective digits aj (j=0, 1, 2, n-1) of n-digit of the operand in K-ary number are given by the vectors consisting of the K picture elements and the values of the respective digits aj are expressed by the spacial positions of the picture elements to allow the passage of light. The black picture elements are the picture elements which do not allow the passage of the light and the white picture elements are the picture elements to allow the passage of the light in the diagram indicating aj in the case of the values being 0, 1, 2...k-2, K-1. The respective digits expressed by this diagram are constituted of the continuation of an arbitrary number (n), by which the operations A of the n-digits are constituted. The desired computation is executed in accordance with the optical computation to convert the two-dimensional arbitrary light input to the two-dimensional arbitrary light output and is executed on the basis of the movement of the light from the arbitrary point on the two dimensions to the arbitrary point on another two dimensions.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式