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91. 发明公开

EP1145443A3 1BIT-DIGITAL-ANALOG-WANDLER-SCHALTUNG 审中-公开
标题翻译： 1BIT数字模拟转换电路
公开(公告)号：EP1145443A3
公开(公告)日：2002-09-11
申请号：EP00920408.2
申请日：2000-03-22
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： KLING, Helmut
IPC分类号： H03M3/02
CPC分类号： H03M3/376 , H03M3/502

92. 发明公开

EP1201026A1 BREAK-BEFORE-MAKE DISTORTION COMPENSATION FOR A DIGITAL AMPLIFIER 审中-公开
标题翻译：失真补偿，且不ÜERLAPPUNGFOR数字放大器
公开(公告)号：EP1201026A1
公开(公告)日：2002-05-02
申请号：EP00952211.1
申请日：2000-07-26
申请人： Tripath Technology, Inc.
发明人： MIAO, Guoqing , DELANO, Cary, L.
IPC分类号： H03F3/38 , H03F21/00 , H03F3/217
CPC分类号： H03F3/2175 , H03F3/2171 , H03M3/376 , H03M3/502
摘要： Methods and apparatus are described for reducing or eliminating break-before-make, i.e. dead time distortion, in switching amplifiers. A switching amplifier (M1, M2) has an input stage (510) for generating a switching signal. Break-before-make distortion compensation circuitry (504) alters the switching signal. Break-before-make generator circuitry (506) generates two drive signals from the altered switching signal. A power stage includes two switches (D1, D2) which are alternately driven by the two drive signals. Break-before-make distortion detection circuitry (502) detects a distortion pattern at the power stage output node and controls the break-before-make distortion compensation circuitry (504) to alter the switching signal in response to the distortion pattern detected to thereby eliminate at least some break-before-make distortion.

93. 发明授权

EP0607712B1 Frequency modulated integrator circuit 失效
标题翻译：频率模块集成商
公开(公告)号：EP0607712B1
公开(公告)日：2001-09-12
申请号：EP93400130.6
申请日：1993-01-20
申请人： SCHLUMBERGER INDUSTRIES S.A.
发明人： Beneteau, Lionel , Gervais, Michel
IPC分类号： G06G7/186 , G06G7/161 , H03M3/02 , H03M1/60 , G01R21/133
CPC分类号： G01R21/133 , G06G7/161 , G06G7/186 , H03M1/60 , H03M3/34 , H03M3/376 , H03M3/43 , H03M3/456

94. 发明公开

EP0506094A3 A semiconductor integrated circuit and a data processor 失效
标题翻译：半导体集成电路和数据处理器
公开(公告)号：EP0506094A3
公开(公告)日：1994-06-15
申请号：EP92105324.5
申请日：1992-03-27
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Akojima, Chikara , Kenmoku, Atuko , Sugino, Kimihiro
IPC分类号： G06J1/00 , H04B3/23
CPC分类号： H03M3/376 , G06J1/00 , H03M3/458
摘要： In a digital-analog hybrid LSI including an analog circuit (2) and a digital circuit (3), the analog circuit (2) includes a circuit for sampling, according to the operation timing of a switch (4), information to be processed by the analog circuit (2) in a capacitor (5). A clock signal generating means (6) generates an operation reference clock signal (b) for the digital circuit (3) so that the change of the clock signal (b) is stopped at a timing when the switch (4) is opened, i.e., during a specified period (T) which includes the high-to-low transition timing of the clock signal. This prevents the analog characteristic of the analog circuit (3) from being degraded by digital noise that is transferred through the junction capacitance of the semiconductor chip (1).

95. 发明公开

EP0506094A2 A semiconductor integrated circuit and a data processor 失效
标题翻译： Halbleiterintegrierte Schaltung和Datenprozessor。
公开(公告)号：EP0506094A2
公开(公告)日：1992-09-30
申请号：EP92105324.5
申请日：1992-03-27
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Akojima, Chikara , Kenmoku, Atuko , Sugino, Kimihiro
IPC分类号： G06J1/00 , H04B3/23
CPC分类号： H03M3/376 , G06J1/00 , H03M3/458
摘要： In a digital-analog hybrid LSI including an analog circuit (2) and a digital circuit (3), the analog circuit (2) includes a circuit for sampling, according to the operation timing of a switch (4), information to be processed by the analog circuit (2) in a capacitor (5). A clock signal generating means (6) generates an operation reference clock signal (b) for the digital circuit (3) so that the change of the clock signal (b) is stopped at a timing when the switch (4) is opened, i.e., during a specified period (T) which includes the high-to-low transition timing of the clock signal. This prevents the analog characteristic of the analog circuit (3) from being degraded by digital noise that is transferred through the junction capacitance of the semiconductor chip (1).
摘要翻译：在包括模拟电路（2）和数字电路（3）的数模混合式LSI中，模拟电路（2）包括根据开关（4）的操作定时对要处理的信息进行采样的电路通过电容器（5）中的模拟电路（2）。时钟信号发生装置（6）产生用于数字电路（3）的操作基准时钟信号（b），使得时钟信号（b）的改变在开关（4）打开的时刻停止，即，在包括时钟信号的从高到低的转换定时的指定周期（T）期间。这防止了通过半导体芯片（1）的结电容传送的数字噪声来降低模拟电路（3）的模拟特性。

96. 发明申请

US20190173486A1 ANALOG TO DIGITAL CONVERTERS WITH OVERSAMPLING 审中-公开
公开(公告)号：US20190173486A1
公开(公告)日：2019-06-06
申请号：US16174088
申请日：2018-10-29
申请人： Avnera Corporation
发明人： Jianping Wen , Ali Hadiashar , Eric King , David Entrikin , Wai Lang Lee
IPC分类号： H03M3/00
CPC分类号： H03M3/496 , H03M3/376 , H03M3/438
摘要： Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

97. 发明申请

US20180183459A1 METASTABILITY COMPENSATION 审中-公开
公开(公告)号：US20180183459A1
公开(公告)日：2018-06-28
申请号：US15849672
申请日：2017-12-21
申请人： NXP B.V.
发明人： Lucien Johannes BREEMS , Muhammed BOLATKALE
IPC分类号： H03M3/00
CPC分类号： H03M3/352 , H03M1/0863 , H03M1/12 , H03M3/344 , H03M3/376 , H03M3/412 , H03M3/458 , H03M3/464
摘要： A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.

98. 发明申请

US20170250703A1 ANALOG TO DIGITAL CONVERTERS WITH OVERSAMPLING 审中-公开
公开(公告)号：US20170250703A1
公开(公告)日：2017-08-31
申请号：US15490759
申请日：2017-04-18
申请人： Avnera Corporation
发明人： Jianping Wen , Ali Hadiashar , Eric King , David Entrikin , Wai Lang Lee
IPC分类号： H03M3/00
CPC分类号： H03M3/496 , H03M3/376 , H03M3/438
摘要： Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

99. 发明授权

US09729165B2 Delta-sigma analog-to-digital converter topology with improved distortion performance 有权
公开(公告)号：US09729165B2
公开(公告)日：2017-08-08
申请号：US15153384
申请日：2016-05-12
申请人： Texas Instruments Incorporated
发明人： Amit K. Gupta , Peng Cao , Venkatesh Acharya
IPC分类号： H03M1/06 , H03M3/00
CPC分类号： H03M3/376 , H03M3/344 , H03M3/422 , H03M3/452
摘要： A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.

100. 发明授权

US09712184B2 Sigma-delta modulator 有权
公开(公告)号：US09712184B2
公开(公告)日：2017-07-18
申请号：US15197398
申请日：2016-06-29
申请人： NXP B.V.
发明人： Lucien Johannes Breems , Muhammed Bolatkale
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
摘要： A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.

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