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91. 发明授权

US06691277B1 High speed pre-computing circuit and method for finding the error-locator polynomial roots in a Reed-Solomon decoder 失效
标题翻译：用于在Reed-Solomon解码器中找到误差定位多项式根的高速预计算电路和方法
公开(公告)号：US06691277B1
公开(公告)日：2004-02-10
申请号：US09190149
申请日：1998-11-12
申请人： Habibollah Golnabi , Inderpal Deol
发明人： Habibollah Golnabi , Inderpal Deol
IPC分类号： H03M1315
CPC分类号： H03M13/1555 , H03M13/1515 , H03M13/155 , H03M13/158
摘要： A system and method used in a Reed-Solomon (RS) decoder for determining roots of error locator polynomials in which a first pre-computation operation is performed to obtain a p-bit polynomial solution value in a first clock cycle and second parallel feedback logical operations are performed to obtain a p-bit polynomial solution value in each subsequent clock cycles. The system excludes constant Galois Field multipliers from the critical timing path of the system so as to facilitate high speed error-locator polynomial root determination. In the case of an unshortened RS(m,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p−1, final root location values are obtained in m cycles. In the case of a shortened RS(n,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p−1 and n
摘要翻译：一种用于确定误差定位多项式的根的Reed-Solomon（RS）解码器的系统和方法，其中执行第一预计算操作以获得第一时钟周期中的p位多项式解值并且第二并行反馈逻辑执行操作以在每个后续时钟周期中获得p位多项式解值。该系统从系统的临界定时路径中排除恒定的伽罗瓦域乘法器，以便于高速误差定位多项式根确定。在Galois Field GF（2））上定义的未经驱动的RS（m，d）解码器的情况下，其中GF（2）是2个元素的有限域，m = 2
-1，最终根位置值以m个周期获得。在Galois Field GF（2）上定义的缩短的RS（n，d）解码器的情况下，其中GF（2）是2个元素的有限域，m = 2
-1和n

92. 发明授权

US06574771B1 Galios field processor having dual parallel data path for Bose Chaudhuri Hocquenghem/Reed-Solomon decoder 失效
标题翻译：用于Bose Chaudhuri Hocquenghem / Reed-Solomon解码器的具有双并行数据路径的Galios现场处理器
公开(公告)号：US06574771B1
公开(公告)日：2003-06-03
申请号：US09528676
申请日：2000-03-20
申请人： Hyung-joon Kwon
发明人： Hyung-joon Kwon
IPC分类号： H03M1300
CPC分类号： H03M13/6561 , H03M13/15 , H03M13/153 , H03M13/1555 , H03M13/158
摘要： A Galois field processor having a dual parallel data path for a Bose Chaudhuri Hocquenghem/Reed-Solomon (BCH/RS) decoder is provided. The Galois field processor includes a syndrome register block for storing syndrome values transmitted by a syndrome generating block, a correction polynomial register block, a connection polynomial register block, and a discrepancy register block. A dual mode Galois field data path (DMGFDP) includes a first data path for receiving the respective outputs of the syndrome register block, the correction polynomial register block, the connection polynomial register block, and the discrepancy register block, performing predetermined operations related to the even-degree coefficients of correction and connection polynomial, and outputting the even-degree coefficient output. A second data path performs predetermined operations related to the odd-degree coefficients of the correction and connection polynomial and outputs the odd-degree coefficient output. A delta output unit performs predetermined operations related to the even-degree and the odd-degree coefficients of the connections polynomial and outputs the delta output. An output unit outputs the coefficients of an error location polynomial, according to a control signal. Since the Galois processor, in which latency during the operation processes is minimized, has a small area and operates at high speed, the performance of the decoder is greatly improved.
摘要翻译：提供了一种具有用于Bose Chaudhuri Hocquenghem / Reed-Solomon（BCH / RS）解码器的双平行数据路径的Galois场处理器。伽罗瓦域处理器包括用于存储由校正子生成块，校正多项式寄存器块，连接多项式寄存器块和差异寄存器块发送的校正子值的校正子寄存器块。双模式伽罗瓦域数据路径（DMGFDP）包括用于接收校正子寄存器块，校正多项式寄存器块，连接多项式寄存器块和差异寄存器块的相应输出的第一数据路径，执行与校正和连接多项式的偶数系数，并输出偶数系数输出。第二数据路径执行与校正连接多项式的奇数系数相关的预定操作，并输出奇数系数输出。增量输出单元执行与连接多项式的偶数和奇数系数相关的预定操作并输出增量输出。输出单元根据控制信号输出误差位置多项式的系数。由于在操作过程中的延迟被最小化的Galois处理器具有小面积并且以高速操作，因此大大提高了解码器的性能。

93. 发明申请

US20030014713A1 Signal processing method, signal processing system, program for signal processing, and computer-readable storage medium on which this program is recorded 失效
公开(公告)号：US20030014713A1
公开(公告)日：2003-01-16
申请号：US10092407
申请日：2002-03-06
申请人： International Business Machines Corporation
发明人： Sumio Morioka , Yasunao Katayama , Toshiyuki Yamane
IPC分类号： H03M013/03
CPC分类号： H03M13/1555 , H03M13/1525
摘要： A signal processing method for a digital signal comprising the steps of: establishing a Yule-Walker equation having the following form by using a matrix that includes, as components, the elements of a Galois field GF(2m), and a vector that includes, as components, the elements of the Galois field GF(2m) 1 ( S 0 S 1 null S l - 1 S 1 S 2 null S l null null null null S l - 1 S l null S 2 null l - 2 ) null ( null l ( l ) null null null 1 ( l ) ) = ( S l null null S 2 null l - 1 ) ; employing Jacobi's formula to obtain the solution of the above equation by the calculation of determination of symmetric matrices; determining the number of errors to be the maximum matrix size that corresponds to the obtained solution that is not zero; and determining whether the number of errors equals the maximum number of correctable errors.

94. 发明授权

US06412090B1 Galois field computation system and method 有权
标题翻译：伽罗瓦域计算系统和方法
公开(公告)号：US06412090B1
公开(公告)日：2002-06-25
申请号：US09336626
申请日：1999-06-18
申请人： Wenwei Pan , Yue-Peng Zheng
发明人： Wenwei Pan , Yue-Peng Zheng
IPC分类号： H03M1315
CPC分类号： H03M13/6516 , H03M13/1515 , H03M13/153 , H03M13/1555
摘要： Disclosed is a configurable Galois field computation system and method, the system comprising a read bus and a write bus with a memory coupled therebetween. In addition, a logical circuit is coupled between the read and write busses, the logical circuit having a number of data calculation configurations that are established to generate an n symbol codeword from a number of symbols in a syndrome array. The logical circuit is placed in the various data calculation configurations in order to perform the various operations involved with Reed-Solomon decoding.
摘要翻译：公开了一种可配置的伽罗瓦域计算系统和方法，该系统包括读总线和写总线，其间耦合有存储器。此外，逻辑电路耦合在读和总线之间，逻辑电路具有多个数据计算配置，其被建立以从校正子阵列中的多个符号生成n个符号码字。将逻辑电路置于各种数据计算配置中，以执行Reed-Solomon解码所涉及的各种操作。

95. 发明授权

US06347389B1 Pipelined high speed reed-solomon error/erasure decoder 有权
标题翻译：流水线高速专用独奏错误/擦除解码器
公开(公告)号：US06347389B1
公开(公告)日：2002-02-12
申请号：US09274406
申请日：1999-03-23
申请人： Keith G. Boyer
发明人： Keith G. Boyer
IPC分类号： H03M1315
CPC分类号： H03M13/1555 , H03M13/1515 , H03M13/154
摘要： The pipelined high speed Reed-Solomon error/erasure decoder processes multiple code words in a pipelined fashion. The pipelined high speed Reed-Solomon error/erasure decoder is designed to process Reed-Solomon encoded words that have been corrupted in a digital system by processing errors as well as erasures through a simple iterative modified syndrome process. The iterative nature of this method provides for limited computational effort at each step of the pipeline. This allows the pipelined high speed Reed-Solomon error/erasure decoder to easily handle full or shortened Reed-Solomon codes, as well as parallel processing to achieve higher data rates. The iterative modified syndrome process is one of the pipelined steps. It relieves the erasure pre-shifting burden from the Berlekamp/Massey synthesis process, which reduces the number of cycles required at that stage of processing. The decoder proceeds classically with a Chien Search for any remaining error locations. This approach allows the pipelined high speed Reed-Solomon error/erasure decoder to relay early information on all error locations. The final stage of the decoding process is a parallel, iterative solution to Forney's equation for the calculation of the error magnitudes.
摘要翻译：流水线高速Reed-Solomon错误/擦除解码器以流水线方式处理多个代码字。流水线高速里德 - 所罗门错误/擦除解码器旨在通过处理错误以及通过简单的迭代修改综合征过程进行擦除来处理在数字系统中损坏的里德 - 所罗门编码的字。该方法的迭代性质在流水线的每个步骤提供有限的计算工作。这允许流水线高速里德 - 所罗门错误/擦除解码器轻松处理完整或缩短的里德 - 所罗门码，以及并行处理以实现更高的数据速率。迭代修正综合征过程是流水线步骤之一。它可以减轻Berlekamp / Massey合成过程中的擦除预先转移负担，从而减少了处理阶段所需的周期数。解码器通过Chien搜索经历了任何剩余的错误位置。这种方法允许流水线高速里德 - 所罗门错误/擦除解码器在所有错误位置上传递早期信息。解码过程的最后阶段是用于计算误差幅度的Forney方程的并行迭代解。

96. 发明授权

EP1175015B1 Decoding circuit and decoding method thereof 有权
标题翻译：解码电路和相关联的解码方法
公开(公告)号：EP1175015B1
公开(公告)日：2009-12-09
申请号：EP01116732.7
申请日：2001-07-18
申请人： NEC CORPORATION
发明人： Seki, Katsutoshi
IPC分类号： H03M13/15
CPC分类号： H03M13/1595 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/153 , H03M13/1535 , H03M13/154 , H03M13/1545 , H03M13/1555 , H03M13/158

97. 发明公开

EP1782542A2 METHODS AND APPARATUS FOR ERROR CORRECTION OF TRANSPARENT GFP (GENERIC FRAMING PROCEDURE) SUPERBLOCKS 审中-公开
标题翻译：方法和设备进行纠错透明GFP超级块
公开(公告)号：EP1782542A2
公开(公告)日：2007-05-09
申请号：EP05791554.8
申请日：2005-08-22
申请人： Transwitch Corporation
发明人： BHATTACHARYA, Santanu, 4, United India Apartment , GUPTA, Neeraj, Residence:4 , MITTAL, Yogesh, k-90, Gyansaravar Colony , DARSHINI, Priya , MUKHOPADHYAY, Suvhasis
IPC分类号： H03M13/15
CPC分类号： H03M13/1555 , H03M13/09 , H03M13/1545 , H03M13/1575
摘要： Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8x8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

98. 发明公开

EP1468499A4 INTRA-DECODER COMPONENT BLOCK MESSAGING 审中-公开
标题翻译： INTRA-解码器组件BLOCK电信
公开(公告)号：EP1468499A4
公开(公告)日：2005-12-14
申请号：EP03732044
申请日：2003-01-22
申请人： THOMSON LICENSING
发明人： LITWIN JR LOUIS ROBERT , VELEZ DIDIER
IPC分类号： G06F11/10 , G11B20/18 , H03M13/15 , H03M13/29 , H04L1/00
CPC分类号： G11B20/1803 , G11B20/10296 , H03M13/1515 , H03M13/1555
摘要： A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator (410), an error polynomial is generated based upon the syndrome in an error polynomial generator (420), an error location is determined from the error polynomial in the error location generator (430), an error magnitude is calculated from the error polynomial in the error magnitude generator (440) and the codeword is corrected by a error corrected codeword generator (450) responsive to location and error magnitude. An intra?decoder block messaging scheme is described in which one or more components (410, 420, 430, 440, 450) generate inactivity messages (640, 650) to signal an ability to process data corresponding to a next codeword. A dual Chien search block (930, 940) implementation is described in which Chien block (930) is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block (940). An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder (1140) to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block (950) implemented with a LIFO register (952).

99. 发明公开

EP1370004A3 Arithmetic unit for Reed-Solomon decoder 失效
标题翻译：对于Reed-Solomon解码运算单元
公开(公告)号：EP1370004A3
公开(公告)日：2005-05-04
申请号：EP03020349.1
申请日：1997-10-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Fukuoka, Toshihiko 15-24 Kiyotaki-Nakamachi , Fukumoto, Yoshihiko , Ohta, Kazuhiro
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/1535 , H03M13/151 , H03M13/1515 , H03M13/1555 , H03M13/158
摘要： A Eucliedan algorithm arithmetic operation system for finding an error locator polynomial σ(z) and an error evaluator polynomial ω(z) from a syndrome polynomial S(z) relative to a t-multiple error correcting Reed-Solomon code, where t is any positive integer, the system comprising: a data storage unit (1)for storing signals representing the syndrome polynomial S(z) and feedback signals representing an intermediate result of a Euclidean algorithm arithmetic operation andfor providing signals representing the error locator polynomial σ(z) and signals representing the error evaluator polynomial ω(z), an arithmetic unit (2) for generating the feedback signals from the signals stored in the data storage unit (1), and a control unit (3) for controlling the data storage unit (1) and the arithmetic unit (2).

100. 发明公开

EP1175015A3 Decoding circuit and decoding method thereof 有权
标题翻译：解码电路和相关联的解码方法
公开(公告)号：EP1175015A3
公开(公告)日：2004-08-04
申请号：EP01116732.7
申请日：2001-07-18
申请人： NEC CORPORATION
发明人： Seki, Katsutoshi
IPC分类号： H03M13/15
CPC分类号： H03M13/1595 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/153 , H03M13/1535 , H03M13/154 , H03M13/1545 , H03M13/1555 , H03M13/158
摘要： A decoding circuit and a decoding method thereof can significantly reduce circuit scale and power consumption. The decoding circuit, in which a plurality of code words are transmitted in interleaved manner and a plurality of code words are simultaneously decoded on reception side, comprises a decoder which decodes a plurality of said code words simultaneously.

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