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91. 发明专利

JP4337964B2 Device for signal processing discrete-time values 有权
公开(公告)号：JP4337964B2
公开(公告)日：2009-09-30
申请号：JP2000535097
申请日：1999-02-18
申请人：ゲーテーエー・ゲゼルシャフト・フューア・テクニッシュ・エントヴィックルンゲン・ゲーエムベーハー
发明人：ヴァイゲル，ラルフ
IPC分类号： H03M1/66 , G06J1/00 , G11B20/10 , H03H17/06 , H03M1/06
CPC分类号： H03M1/662 , G06J1/00 , G11B20/10527 , H03M1/0643

92. 发明专利

JP2008512879A Digital-to-analog converter 有权
公开(公告)号：JP2008512879A
公开(公告)日：2008-04-24
申请号：JP2007511143
申请日：2005-10-21
申请人：シャープ株式会社
发明人：パトリックゼベダイ， , ジェレミーロック，
IPC分类号： H03M1/74 , G02F1/133 , G09G3/20 , G09G3/36 , H03M1/10 , H03M1/66
CPC分类号： H03M1/1061 , H03M1/662
摘要：デジタルアナログ変換器（３３）は、同じ個数の双方向バッファレス型デジタルアナログ変換器（６，６'）の第１のグループと第２のグループとを備える。各グループにおける少なくとも１つの変換器の出力は、容量性の負荷（Ｃ
ＬＯＡＤ，Ｃ
ＬＯＡＤ' ）のそれぞれに接続される。動作の較正フェーズの間、変換器の入力は、同じ出力レベルを表す第１および第２の異なるコードを受信する。変換器（３３）はまた、各変換器出力に接続されたスイッチ式キャパシタネットワーク（７，７'）のそれぞれと、第１および第２のグループの出力電圧を比較するためのコンパレータ（８）と、制御回路（９）とを備える。制御回路（９）は、第１および第２のグループの出力電圧を実質的に等しくするように、コンパレータに応答して、キャパシタネットワーク（７，７'）を制御する。

93. 发明专利

JP2007324895A Digital/analog converter and transmitter 有权
标题翻译：数字/模拟转换器和发送器
公开(公告)号：JP2007324895A
公开(公告)日：2007-12-13
申请号：JP2006152479
申请日：2006-05-31
申请人： Toshiba Corp , 株式会社東芝
发明人： UENO TAKESHI , YAMAJI TAKAFUMI
IPC分类号： H03M1/08
CPC分类号： H03M1/662 , H04B1/0483 , H04B14/04
摘要： PROBLEM TO BE SOLVED: To suppress the discrepancy in analog conversion accuracy of a digital multidimensional signal such as a complex signal.
SOLUTION: This digital/analog converter is provided with: a decoder (decoder 101 in the selected figure) for converting an input digital signal of an (n-1)-phase into an output digital signal of an n-phase; n pieces of analog output signal generation circuits (e.g. transistor 111-01, 111-2 to 111-m and resistor 141 configure an analog voltage generation circuit for one phase in the selected figure) for respectively generating analog signals of magnitudes corresponding to respective phases of the output digital signal.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：抑制诸如复数信号的数字多维信号的模拟转换精度的差异。解决方案：该数字/模拟转换器具有：用于将（n-1）相的输入数字信号转换为n相的输出数字信号的解码器（所选图中的解码器101） n个模拟输出信号发生电路（例如，晶体管111-01,111-2至111-m和电阻器141配置所选图中的一相的模拟电压产生电路），用于分别产生对应于相位的幅度的模拟信号的输出数字信号。版权所有（C）2008，JPO＆INPIT

94. 发明专利

JP2004272191A Data driving circuit 审中-公开
公开(公告)号：JP2004272191A
公开(公告)日：2004-09-30
申请号：JP2003180055
申请日：2003-06-24
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： SUN WEIN-TOWN
IPC分类号： H01L51/50 , G09G3/20 , G09G3/30 , G09G3/32 , H03M1/06 , H03M1/66 , H05B33/14
CPC分类号： G09G3/3283 , G09G3/3216 , G09G3/3241 , G09G2310/027 , G09G2310/0289 , H03M1/0607 , H03M1/662
摘要： PROBLEM TO BE SOLVED: To provide a data driving circuit having a current storing and replicating function and containing a current storing and replicating module leading replicated current signals in a reproducing/ adjusting stage, to resolve a problem of stability in the conventional technic. SOLUTION: This data driving circuit 30 includes a digital/ analog current converter 38 converting received digital signals into analog current signals; a current storing and replicating module 42 storing a schedule voltage required to lead the analog current signals in a converting/storing stage, and leading the replicated current signals into data lines in a reproducing/adjusting stage; and a control circuit electrically connected between the converter 38 and the module 42 and switching between the converting/storing stage and reproducing/adjusting stage. The replicated current signals are gray scale current signals, being almost same as the analog current signals. COPYRIGHT: (C)2004,JPO&NCIPI

95. 发明申请

WO2016122914A1 DISTRIBUTED COMBINER FOR PARALLEL DISCRETE-TO-LINEAR CONVERTERS 审中-公开
标题翻译：用于并联离散线性转换器的分布式组合器
公开(公告)号：WO2016122914A1
公开(公告)日：2016-08-04
申请号：PCT/US2016/013756
申请日：2016-01-16
申请人： SYNTROPY SYSTEMS, LLC
发明人： PAGNANELLI, Christopher
IPC分类号： H03M1/08 , H03F3/21 , H03M1/66
CPC分类号： H03M1/661 , H03F3/211 , H03M1/08 , H03M1/0836 , H03M1/662 , H03M3/30 , H03M3/50
摘要： Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals ( i.e ., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal.
摘要翻译：除其他之外，提供了用于从一组部分信号提供完整的输出信号的系统，装置方法和技术，这些部分信号又在离散的时间交织和/或频率交织的转换中由并行处理路径产生信号到线性信号（即离散到线性转换）。一种这样的设备包括分布式网络，其包括多个梯形网络，输入信号在组合之前通过该梯形网络传播以形成输出信号。

96. 发明申请

WO2016040597A1 HYBRID MODULATOR UTILIZING DIGITAL DOMAIN MULTIPLEXING 审中-公开
标题翻译：混合调制器利用数字域多路复用
公开(公告)号：WO2016040597A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/049379
申请日：2015-09-10
申请人： GATESAIR, INC.
发明人： ILSEN, Stefan , ROTHER, Daniel
IPC分类号： H04L27/00 , H04L5/22
CPC分类号： H03M1/662 , H04H20/28 , H04H20/72 , H04N21/2383
摘要： Systems and methods are provided for generating a hybrid signal. A first signal source is configured to provide a first digital signal having a first sample rate, and a second signal source is configured to provide a second digital signal having a second sample rate. A resampling component is configured to resample the second digital signal into a resampled signal having the first sample rate. A multiplexing component is configured to combine the first digital signal and the resampled signal into a multiplexed signal. A digital-to-analog converter is configured to convert the multiplexed signal into an analog signal.
摘要翻译：提供了用于产生混合信号的系统和方法。第一信号源被配置为提供具有第一采样率的第一数字信号，并且第二信号源被配置为提供具有第二采样率的第二数字信号。重采样组件被配置为将第二数字信号重新采样成具有第一采样率的重采样信号。复用分量被配置为将第一数字信号和重采样信号组合成多路复用信号。数模转换器被配置为将复用的信号转换为模拟信号。

97. 发明申请

WO2015160655A1 SWITCHABLE SECONDARY PLAYBACK PATH 审中-公开
标题翻译：可切换二级回放路径
公开(公告)号：WO2015160655A1
公开(公告)日：2015-10-22
申请号：PCT/US2015/025329
申请日：2015-04-10
申请人： CIRRUS LOGIC, INC.
发明人： DAS, Tejasvi , MELANSON, John L. , TUCKER, John, C. , FEI, Xiaofan
IPC分类号： H03M1/00 , H03M1/66 , H03M1/68 , H03M1/70
CPC分类号： H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
摘要翻译：根据本公开的实施例，处理系统可以包括多个处理路径，包括第一处理路径和第二处理路径，数模转换阶段输出和控制器。第一处理路径可以包括用于将数字输入信号转换成第一中间模拟信号的第一数模转换器，第一数模转换器被配置为在大功率状态和低功率状态。第二处理路径可以包括用于将数字输入信号转换成第二中间模拟信号的第二数模转换器。数模转换级输出可以被配置为产生包括第一中间模拟信号和第二中间模拟信号之和的模拟信号。控制器可以被配置为当数字输入信号的幅度低于阈值大小时，在较低功率状态下操作第一数模转换器。

98. 发明申请

WO2012096776A1 POLYPHASE NONLINEAR DIGITAL PREDISTORTION 审中-公开
标题翻译：多项非线性数字预测
公开(公告)号：WO2012096776A1
公开(公告)日：2012-07-19
申请号：PCT/US2011/066768
申请日：2011-12-22
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , GOODMAN, Joel, I. , MILLER, Benjamin, A. , HERMAN, Matthew, A. , VIAN, James, Edwin
发明人： GOODMAN, Joel, I. , MILLER, Benjamin, A. , HERMAN, Matthew, A. , VIAN, James, Edwin
IPC分类号： H03M1/06 , H03M1/10
CPC分类号： H03M1/0626 , H03M1/0614 , H03M1/1052 , H03M1/662
摘要： Polyphase nonlinear digital predistorters (pNDPs) mitigate nonlinear distortions generated by time-interleaved digital-to-analog converters (TIDACs). Processors in an example pNDP compute nonlinear and linear compensation terms representative of channel mismatches and other imperfections in the TIDAC based on the digital input to the TIDAC. The pNDP subtracts these compensation terms from a delayed copy of the digital input to yield a predistorted digital input. The TIDAC converts on the predistorted digital input into a fullband analog output that is substantially free of nonlinear distortion.
摘要翻译：多相非线性数字预失真器（pNDP）减轻了由时间交错的数模转换器（TIDAC）产生的非线性失真。示例中的处理器pNDP基于对TIDAC的数字输入来计算表示TIDAC中的信道不匹配和其他缺陷的非线性和线性补偿项。 pNDP从数字输入的延迟拷贝中减去这些补偿项，以产生预失真的数字输入。 TIDAC将预失真的数字输入转换为完全没有非线性失真的全频模拟输出。

99. 发明申请

WO2009073733A1 REFERENCE VOLTAGE GENERATION IN IMAGING SENSORS 审中-公开
标题翻译：成像传感器参考电压产生
公开(公告)号：WO2009073733A1
公开(公告)日：2009-06-11
申请号：PCT/US2008/085420
申请日：2008-12-03
申请人： ALTASENS, INC. , ROSSI, Giuseppe , BLANQUART, Laurent , HUANG, Ying
发明人： ROSSI, Giuseppe , BLANQUART, Laurent , HUANG, Ying
IPC分类号： H04N5/335
CPC分类号： H03M1/662 , H03M1/76 , H04N5/335 , H04N5/3698
摘要： The claimed subject matter provides systems and/or methods that facilitate generating and/or maintaining low noise reference voltages for CMOS imaging System-on-Chip (iSoC) sensors. A primary reference voltage can be generated utilizing a low noise bandgap. Further, the primary reference voltage can be filtered via a low pass filter. The filtered, primary reference voltage can thereafter be distributed to a plurality of isolated domains. Each of the isolated domains can generate an independent set of reference voltages based upon the filtered, primary reference voltage. Moreover, subsets of these reference voltages can be employed by programmable digital to analog converters (DACs). Each of the reference voltages can be isolated from switching noise and/or clock glitches generated within each domain. Further, each DAC output can be buffered to have adequately low impedance with appropriate drive capability and requisite signal swing.
摘要翻译：所要求保护的主题提供了有助于为CMOS成像片上系统（iSoC）传感器产生和/或维持低噪声参考电压的系统和/或方法。可以利用低噪声带隙产生主参考电压。此外，可以通过低通滤波器对初级参考电压进行滤波。滤波后的主参考电压此后可以分配到多个隔离域。每个隔离域可以基于滤波的主要参考电压产生独立的一组参考电压。此外，这些参考电压的子集可由可编程数模转换器（DAC）采用。每个参考电压可以与每个域内产生的开关噪声和/或时钟故障隔离。此外，每个DAC输出可以被缓冲以具有适当的低阻抗，具有适当的驱动能力和必要的信号摆幅。

100. 发明申请

WO2008155301A2 DIRECT RF D-TO-A CONVERSION 审中-公开
标题翻译：直接RF D转换
公开(公告)号：WO2008155301A2
公开(公告)日：2008-12-24
申请号：PCT/EP2008/057521
申请日：2008-06-16
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , DENT, Paul Wilkinson , KLEMMER, Nikolaus
发明人： DENT, Paul Wilkinson , KLEMMER, Nikolaus
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/662 , H03M3/41 , H03M3/502
摘要： A modulator described herein provides digital modulation and direct digital-to-analog conversion capable of achieving 12-bit resolution or higherfor high frequency signals. The modulator comprises a digital modulator, conversion circuit, and multiplexer. The digital modulator generates a plurality of sample streams at a plurality of different sample phases that collectively represent a desired modulated digital carrier waveform modulated by a digital input signal. The conversion circuit converts the sample streams into a plurality of continuous analog signals. The multiplexer multiplexes the analog signals together to generate a modulated analog carrier signal representative of the desired modulated digital carrier waveform.
摘要翻译：本文所述的调制器提供能够实现12位分辨率或更高的高频信号的数字调制和直接数模转换。调制器包括数字调制器，转换电路和多路复用器。数字调制器在多个不同的采样相位产生多个样本流，它们共同表示由数字输入信号调制的期望的调制数字载波波形。转换电路将采样流转换为多个连续的模拟信号。多路复用器将模拟信号复用在一起以产生表示所需调制数字载波波形的调制模拟载波信号。

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