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91. 发明申请

US20150155039A1 Three-Dimensional Flash NOR Memory System With Configurable Pins 审中-公开
标题翻译：具有可配置引脚的三维闪存NOR存储器系统
公开(公告)号：US20150155039A1
公开(公告)日：2015-06-04
申请号：US14094595
申请日：2013-12-02
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G11C7/1045 , G11C7/1057 , G11C16/04 , G11C2207/105 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1435 , H01L2924/1438 , H01L2924/15311 , H01L2924/157
摘要： A three-dimensional NOR flash memory system is disclosed. The system optionally comprises configurable standard pins, a configurable output buffer, and a configurable input buffer.
摘要翻译：公开了一种三维NOR闪存系统。该系统可选地包括可配置标准引脚，可配置输出缓冲器和可配置输入缓冲器。

92. 发明申请

US20150084205A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：芯片包装及其形成方法
公开(公告)号：US20150084205A1
公开(公告)日：2015-03-26
申请号：US14034975
申请日：2013-09-24
申请人： NANYA TECHNOLOGY CORPORATION
发明人： PO CHUN LIN
IPC分类号： H01L23/538 , H01L21/768 , H01L23/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5384 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05553 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/0616 , H01L2224/06181 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/10253 , H01L2924/12042 , H01L2924/1435 , H01L2224/03 , H01L2924/014 , H01L2924/00
摘要： A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further comprises a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.
摘要翻译：半导体器件包括用于连接另一半导体器件的多个导体。每个导体通过形成在衬底上形成的绝缘层或连接到通过衬底和绝缘层形成的直立垂直连接的上垂直连接而连接到半导体器件内的芯片选择焊盘。半导体器件还包括通过衬底形成的多个下垂直连接，并且相应地连接到芯片选择焊盘和芯片选择端。芯片选择端子电连接到半导体器件的管芯电路，而芯片选择焊盘与裸片电路电隔离。下垂直连接和垂直垂直连接可以在两个方面布置。

93. 发明申请

US20150048465A1 SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM) 有权
标题翻译：用于磁阻随机存取存储器（MRAM）的小型磁阻电磁屏蔽
公开(公告)号：US20150048465A1
公开(公告)日：2015-02-19
申请号：US14499027
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Shiqun Gu , Rongtian Zhang , Vidhya Ramachandran , Dong Wook Kim
IPC分类号： H01L43/12 , H01L27/22 , H01L43/02
CPC分类号： H01L43/12 , H01L23/3121 , H01L23/552 , H01L23/645 , H01L27/222 , H01L27/228 , H01L43/02 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16227 , H01L2924/0002 , H01L2924/1435 , H01L2924/157 , H01L2924/15788 , H01L2924/3025 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
摘要翻译：一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。通孔包括铁磁材料。在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。在一些实施方案中，通孔通过衬底通孔。在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。

94. 发明授权

US08884423B2 Image forming apparatus, chip, and chip package 有权
标题翻译：图像形成装置，芯片和芯片封装
公开(公告)号：US08884423B2
公开(公告)日：2014-11-11
申请号：US12485369
申请日：2009-06-16
申请人： Seung-hun Park , Eun-ju Hong
发明人： Seung-hun Park , Eun-ju Hong
IPC分类号： H01L23/52 , H01L27/146 , H01L23/50 , H01L23/498
CPC分类号： H01L23/50 , H01L23/49816 , H01L24/09 , H01L24/48 , H01L24/49 , H01L25/167 , H01L27/14618 , H01L2224/05554 , H01L2224/45139 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/48237 , H01L2224/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/1435 , H01L2924/1438 , H01L2924/145 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals.
摘要翻译：一种图像形成装置，包括用于执行图像形成操作的引擎单元和用于控制引擎单元的板单元。板单元包括至少一个包括芯片的芯片封装。芯片包括用于传输第一类型的信号的第一焊盘，用于传输第二类型的信号的第二焊盘以及置于第一和第二焊盘之间的第三焊盘，以减少第一和第二类型的信号之间的串扰。

95. 发明申请

US20130009286A1 SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME 审中-公开
标题翻译：半导体芯片和包含其的片式芯片封装
公开(公告)号：US20130009286A1
公开(公告)日：2013-01-10
申请号：US13471735
申请日：2012-05-15
申请人： Young-lyong Kim , Jong-ho Lee , Moon-gi Cho , Hwan-sik Lim , Sun-hee Park
发明人： Young-lyong Kim , Jong-ho Lee , Moon-gi Cho , Hwan-sik Lim , Sun-hee Park
IPC分类号： H01L23/58
CPC分类号： H01L24/11 , H01L23/3128 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L2224/02123 , H01L2224/0331 , H01L2224/0332 , H01L2224/0345 , H01L2224/03464 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05022 , H01L2224/05024 , H01L2224/05025 , H01L2224/05026 , H01L2224/05027 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05166 , H01L2224/0519 , H01L2224/05191 , H01L2224/05556 , H01L2224/05558 , H01L2224/05559 , H01L2224/0556 , H01L2224/05562 , H01L2224/05568 , H01L2224/05666 , H01L2224/0569 , H01L2224/05691 , H01L2224/1131 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/13191 , H01L2224/14131 , H01L2224/1416 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/1435 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.
摘要翻译：半导体芯片包括减轻压力以减轻印刷电路板（PCB）和半导体芯片之间的热膨胀系数（CTE）的差异以及包括半导体芯片的倒装芯片封装的影响。半导体芯片包括耦合凸块的应力消除缓冲器和半导体芯片焊盘。

96. 发明申请

US20120267796A1 FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES 有权
标题翻译： FLIP-CHIP，FACE-UP和FACE-DOWN CENTREBOND MEMORY WIREBOND ASSEMBLIES
公开(公告)号：US20120267796A1
公开(公告)日：2012-10-25
申请号：US13306099
申请日：2011-11-29
申请人： Belgacem Haba , Richard Dewitt Crisp , Wael Zohni
发明人： Belgacem Haba , Richard Dewitt Crisp , Wael Zohni
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06135 , H01L2224/06136 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29101 , H01L2224/29191 , H01L2224/32145 , H01L2224/32225 , H01L2224/32227 , H01L2224/32245 , H01L2224/45099 , H01L2224/48095 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/48472 , H01L2224/4911 , H01L2224/49112 , H01L2224/49175 , H01L2224/73203 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/06575 , H01L2225/06589 , H01L2225/1023 , H01L2225/1029 , H01L2225/1047 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1431 , H01L2924/1433 , H01L2924/1435 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443 , H01L2924/14511 , H01L2924/15151 , H01L2924/15165 , H01L2924/1517 , H01L2924/15172 , H01L2924/15182 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.
摘要翻译：微电子组件可以包括具有第一和第二表面的基板和在其间延伸的孔，该基板具有端子。组件还可以包括具有面向衬底的第一表面的前表面的第一微电子元件，具有面向第一微电子元件并且突出超过第一微电子元件的边缘的前表面的第二微电子元件，第一和第二引线电将相应的第一和第二微电子元件的触点连接到端子，以及第三引线将第一和第二微电子元件的触点电互连。第一微电子元件的触点可以在靠近其边缘的前表面暴露。第二微电子元件的触点可以设置在其前表面的中心区域中。第一，第二和第三引线可以具有与孔对准的部分。

97. 发明授权

US06880242B2 Method for circuit protection during radiation sterilization 失效
标题翻译：辐射灭菌过程中电路保护方法
公开(公告)号：US06880242B2
公开(公告)日：2005-04-19
申请号：US10382443
申请日：2003-03-06
申请人： William P. Van Antwerp , Sheana Karre , Adrian Prokop , Sara Akiko Stinson , Jason Fong , James J. Rosenberg
发明人： William P. Van Antwerp , Sheana Karre , Adrian Prokop , Sara Akiko Stinson , Jason Fong , James J. Rosenberg
IPC分类号： A61L2/08 , A61L2/26 , H05K3/30
CPC分类号： A61L2/087 , A61L2/081 , A61L2/082 , A61L2/26 , A61L2202/24 , H01L23/556 , H01L25/0655 , H01L2924/0002 , H01L2924/1435 , H01L2924/1438 , H01L2924/145 , Y10T29/49117 , Y10T29/4913 , Y10T29/49137 , Y10T29/49144 , H01L2924/00
摘要： A circuit protection device for protection of sensitive components during high energy radiation sterilization that includes a support substrate and a protective housing. The substrate supports the sensitive components. The protective housing is hermetically coupled to the support substrate to seal the sensitive components within the protective housing. Preferably, the protective housing stops high energy used in the high energy sterilization from damaging the sensitive components from a predetermined exposure level of high energy sterilization. The circuit protection device may further include a protective conductor that is coupled to the support substrate on a side which is opposite the protective housing to prevent high energy from entering the opposite side of the support substrate. The circuit protection device can also include an energy absorbing material contained within an area sealed by the protective housing to absorb high energy byproducts produced by the protective housing stopping the high energy used in the high energy sterilization. Preferably, the support substrate is a circuit board, and the sensitive elements are semiconductors. Also, the high energy sterilization is E-beam sterilization and the high energy are electrons, and the high energy byproducts are x-rays.
摘要翻译：一种用于在包括支撑基板和保护壳体的高能量辐射灭菌期间保护敏感部件的电路保护装置。基板支持敏感元件。保护壳体气密地联接到支撑基板上以密封保护壳体内的敏感部件。优选地，保护壳体阻止在高能量灭菌中使用的高能量，以从高能量灭菌的预定暴露水平损坏敏感部件。电路保护装置还可以包括保护导体，该保护导体在与保护壳体相对的一侧耦合到支撑基板，以防止高能量进入支撑基板的相对侧。电路保护装置还可以包括容纳在由保护壳体密封的区域内的能量吸收材料，以吸收由保护壳体产生的高能量副产品，从而阻止在高能量灭菌中使用的高能量。优选地，支撑衬底是电路板，并且敏感元件是半导体。此外，高能消毒是电子束灭菌，高能量是电子，高能量副产物是X射线。

98. 发明授权

US06828656B2 High performance silicon contact for flip chip and a system using same 失效
标题翻译：用于倒装芯片的高性能硅触点和使用相同的系统
公开(公告)号：US06828656B2
公开(公告)日：2004-12-07
申请号：US10417222
申请日：2003-04-17
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L2940
CPC分类号： H05K1/0222 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L2223/6622 , H01L2924/0002 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/1432 , H01L2924/1435 , H01L2924/145 , H01L2924/15311 , H01L2924/157 , H05K1/115 , H05K2201/09036 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.
摘要翻译：本发明提供一种半导体衬底，其包括前表面和后表面以及延伸穿过衬底并且在前表面和后表面之间的孔。孔部分地由内壁部分限定并形成外导电护套。导电材料靠近内壁部分的至少一部分形成。随后，在孔内，导电材料的上部和内部形成介电材料层。然后在电介质材料层的上方和径向向内的孔内形成第二导电材料。后一导电材料构成内导电同轴线组件。

99. 发明授权

US06812137B2 Method of forming coaxial integrated circuitry interconnect lines 失效
标题翻译：形成同轴集成电路互连线的方法
公开(公告)号：US06812137B2
公开(公告)日：2004-11-02
申请号：US10197554
申请日：2002-07-18
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L214763
CPC分类号： H05K1/0222 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L2223/6622 , H01L2924/0002 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/1432 , H01L2924/1435 , H01L2924/145 , H01L2924/15311 , H01L2924/157 , H05K1/115 , H05K2201/09036 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.
摘要翻译：本发明提供一种半导体衬底，其包括前表面和后表面以及延伸穿过衬底并且在前表面和后表面之间的孔。孔部分地由内壁部分限定并形成外导电护套。导电材料靠近内壁部分的至少一部分形成。随后，在孔内，导电材料的上部和内部形成介电材料层。然后在电介质材料层的上方和径向向内的孔内形成第二导电材料。后一导电材料构成内导电同轴线组件。

100. 发明申请

US20020175423A1 High performance silicon contact for flip chip 失效
公开(公告)号：US20020175423A1
公开(公告)日：2002-11-28
申请号：US10197554
申请日：2002-07-18
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L021/48 , H01L023/52 , H01L029/40
CPC分类号： H05K1/0222 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L2223/6622 , H01L2924/0002 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/1432 , H01L2924/1435 , H01L2924/145 , H01L2924/15311 , H01L2924/157 , H05K1/115 , H05K2201/09036 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.

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