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91. 发明授权

US08975175B1 Solderable contact regions 有权
标题翻译：可焊接触点区域
公开(公告)号：US08975175B1
公开(公告)日：2015-03-10
申请号：US13930668
申请日：2013-06-28
申请人： SunPower Corporation
发明人： Thomas Pass
IPC分类号： H01L21/44 , H01L21/322 , H01L21/265 , H01L21/8238 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/40 , H01L24/84 , H01L31/022425 , H01L31/05 , H01L31/0504 , H01L33/62 , H01L2224/0332 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03515 , H01L2224/03848 , H01L2224/04034 , H01L2224/05011 , H01L2224/05012 , H01L2224/05023 , H01L2224/05078 , H01L2224/0529 , H01L2224/05294 , H01L2224/05324 , H01L2224/05551 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05562 , H01L2224/05567 , H01L2224/05601 , H01L2224/05611 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0566 , H01L2224/05664 , H01L2224/05669 , H01L2224/05671 , H01L2224/05673 , H01L2224/05676 , H01L2224/05794 , H01L2224/05839 , H01L2224/40499 , H01L2224/84203 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/1203 , H01L2924/12041 , Y02E10/50 , H01L2924/00012 , H01L2924/01048 , H01L2924/014 , H01L2224/37099
摘要： A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.
摘要翻译：公开了一种用于半导体衬底的接触区域。实施例可以包括在半导体衬底上形成具有暴露的焊盘区域的种子金属层，并在种子金属层上形成第一金属层。在一个实施例中，在形成第一金属层之前，可以在暴露的焊盘区域上形成诸如银的可焊接材料。实施例可以包括在形成第一金属层之后在暴露的焊盘区域上形成可焊接材料。实施例还可以包括在种子金属层上形成电镀接触区域，其中电镀接触区域允许电镀过程中的导电。

92. 发明申请

US20140061900A1 SEMICONDUCTOR PACKAGE WITH IMPROVED REDISTRIBUTION LAYER DESIGN AND FABRICATING METHOD THEREOF 有权
标题翻译：具有改进的重新分配层设计的半导体封装及其制造方法
公开(公告)号：US20140061900A1
公开(公告)日：2014-03-06
申请号：US13955422
申请日：2013-07-31
申请人： No Sun Park , Ji Yeon Ryu , Go Woon Jung
发明人： No Sun Park , Ji Yeon Ryu , Go Woon Jung
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02123 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/02375 , H01L2224/0347 , H01L2224/0401 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05018 , H01L2224/05024 , H01L2224/05078 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05557 , H01L2224/05558 , H01L2224/05568 , H01L2224/05647 , H01L2224/06051 , H01L2224/06137 , H01L2224/10 , H01L2224/13027 , H01L2224/13028 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.
摘要翻译：公开了具有改进的再分布层设计及其制造方法的半导体封装，并且可以包括半导体管芯，其包括接合焊盘，形成在半导体管芯上的第一再分配层（RDL）。第一RDL具有耦合到接合焊盘的第一端和通过下凸块金属层耦合到焊料凸块的第二端。第二RDL形成在与第一RDL相同的半导体管芯的平面中，并且与第一RDL电隔离。第二RDL的第一端可以耦合到接合焊盘，并且第二RDL可以在下面通过，但是与焊料凸块电隔离。可以在露出第一RDL的第二端的第一和第二RDL上形成钝化层。底部凸块金属层可以形成在由钝化层暴露的第一RDL的第二端上。

93. 发明申请

US20140042593A1 SEMICONDUCTOR DEVICE INCLUDING A TRENCH IN A SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体衬底中包括铁素体的半导体器件和制造半导体器件的方法
公开(公告)号：US20140042593A1
公开(公告)日：2014-02-13
申请号：US13571455
申请日：2012-08-10
申请人： Anton Mauder , Reinhard Ploss , Hans-Joachim Schulze
发明人： Anton Mauder , Reinhard Ploss , Hans-Joachim Schulze
IPC分类号： H01L29/06 , H01L21/225 , H01L29/36
CPC分类号： H01L29/4236 , H01L21/2225 , H01L21/2251 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/28079 , H01L21/30604 , H01L21/324 , H01L21/3247 , H01L21/743 , H01L23/36 , H01L24/05 , H01L29/0653 , H01L29/0657 , H01L29/0878 , H01L29/1079 , H01L29/167 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/4958 , H01L29/66333 , H01L29/66348 , H01L29/66666 , H01L29/66712 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/7827 , H01L2224/05009 , H01L2224/05078 , H01L2224/0557 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side.
摘要翻译：半导体器件包括半导体衬底。第一沟槽从第一侧延伸进入或穿过半导体衬底。半导体层在第一侧邻接半导体衬底。半导体层在第一侧覆盖第一沟槽。半导体器件还包括在与第一侧相对的半导体衬底的第二侧的接触。

94. 发明授权

US07703199B2 Method to accommodate increase in volume expansion during solder reflow 失效
标题翻译：适应焊料回流期间体积膨胀增加的方法
公开(公告)号：US07703199B2
公开(公告)日：2010-04-27
申请号：US11440316
申请日：2006-05-24
申请人： David Vincent Caletka , Krishna Darbha , Donald W. Henderson , Lawrence P. Lehman , George Henry Thiel
发明人： David Vincent Caletka , Krishna Darbha , Donald W. Henderson , Lawrence P. Lehman , George Henry Thiel
IPC分类号： H05K3/30
CPC分类号： H01L23/49811 , B23K3/0623 , B23K2101/40 , H01L21/563 , H01L23/13 , H01L23/49838 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05017 , H01L2224/05026 , H01L2224/05078 , H01L2224/05551 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81385 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/15787 , H05K1/113 , H05K3/284 , H05K3/3436 , H05K2201/0116 , H05K2201/0133 , H05K2201/0382 , H05K2201/068 , H05K2201/09036 , H05K2201/09509 , H05K2201/0969 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , Y10T29/49146 , Y10T29/49149 , Y10T29/49171 , H01L2924/00011 , H01L2924/00 , H01L2224/29099 , H01L2224/05552
摘要： Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
摘要翻译：诸如低熔点C4焊球的焊球在回流期间经历体积膨胀。当焊球被封装时，膨胀压力可能会损坏器件的完整性。每个焊球下方的半导体芯片基板中的体积扩展区容纳体积膨胀。可以使用气垫缓冲图，可变形材料和不可润湿的表面，以允许在冷却期间焊料返回到其原始位置。也可以使用具有足以适应膨胀的空隙的多孔介质。

95. 发明授权

US07086147B2 Method of accommodating in volume expansion during solder reflow 失效
标题翻译：在回流焊时容纳体积膨胀的方法
公开(公告)号：US07086147B2
公开(公告)日：2006-08-08
申请号：US10768836
申请日：2004-01-29
申请人： David Vincent Caletka , Krishna Darbha , Donald W. Henderson , Lawrence P. Lehman , George Henry Thiel
发明人： David Vincent Caletka , Krishna Darbha , Donald W. Henderson , Lawrence P. Lehman , George Henry Thiel
IPC分类号： H05K3/34 , H01L23/48
CPC分类号： H01L23/49811 , B23K3/0623 , B23K2101/40 , H01L21/563 , H01L23/13 , H01L23/49838 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05017 , H01L2224/05026 , H01L2224/05078 , H01L2224/05551 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81385 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/15787 , H05K1/113 , H05K3/284 , H05K3/3436 , H05K2201/0116 , H05K2201/0133 , H05K2201/0382 , H05K2201/068 , H05K2201/09036 , H05K2201/09509 , H05K2201/0969 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , Y10T29/49146 , Y10T29/49149 , Y10T29/49171 , H01L2924/00011 , H01L2924/00 , H01L2224/29099 , H01L2224/05552
摘要： Solder balls such as, low melt C4 solder balls, undergo volume expansion during reflow, such as may occur during attachment of chip modules to a PCB. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodated this volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
摘要翻译：诸如低熔点C4焊球的焊球在回流期间经历体积膨胀，例如在将芯片模块附接到PCB期间可能发生。当焊球被封装时，膨胀压力可能会损坏器件的完整性。在每个焊球下方的半导体芯片基板中的体积膨胀区容纳该体积膨胀。可以使用气垫缓冲图，可变形材料和不可润湿的表面，以允许在冷却期间焊料返回到其原始位置。也可以使用具有足以适应膨胀的空隙的多孔介质。

96. 发明公开

KR1020160019596A 반도체 패키지 审中-实审
标题翻译： SEMICONDUCTRO PACAKAGE
公开(公告)号：KR1020160019596A
公开(公告)日：2016-02-22
申请号：KR1020140103781
申请日：2014-08-11
申请人： 삼성전자주식회사
发明人： 양병완 , 김성훈
IPC分类号： H01L23/49 , H01L23/492
CPC分类号： H01L23/49838 , H01L22/32 , H01L23/49811 , H01L23/49827 , H01L23/522 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05078 , H01L2224/05554 , H01L2224/05567 , H01L2224/06135 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/1434 , H01L2924/1438 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： 본발명의반도체패키지는접속패드를포함하는기판, 제1 반도체칩, 및도전성와이어를포함한다. 상기제1 반도체칩은상기기판상에적층되고, 일측중심부에구비된라우팅영역, 본딩패드들, 및비본딩패드들을포함한다. 상기도전성와이어는상기본딩패드들및 상기접속패드에연결된다. 상기본딩패드들은상기제1 반도체칩의상기일측의연장방향을따라적어도하나의열을이루며상기라우팅영역상에배치되지않는다. 상기비본딩패드들은상기본딩패드들과서로다른열을이루도록배치된다.
摘要翻译：半导体封装包括：包括连接焊盘的衬底; 第一半导体芯片; 和导线。第一半导体芯片堆叠在基板上，并且包括接合焊盘，非接合焊盘和安装在第一半导体芯片的一侧的中心部分中的布线区域。导线连接到接合焊盘和连接焊盘。接合焊盘被布置成在第一半导体芯片的一侧延伸的方向上形成至少一个列，并且不布置在布线区域中。非接合焊盘被布置成形成与焊盘不同的列。

97. 发明授权

KR101429347B1 반도체 패키지 및 그 제조 방법 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：KR101429347B1
公开(公告)日：2014-08-12
申请号：KR1020120095947
申请日：2012-08-30
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 박노선 , 유지연 , 정고운
IPC分类号： H01L23/488
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02123 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/02375 , H01L2224/0347 , H01L2224/0401 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05018 , H01L2224/05024 , H01L2224/05078 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05557 , H01L2224/05558 , H01L2224/05568 , H01L2224/05647 , H01L2224/06051 , H01L2224/06137 , H01L2224/10 , H01L2224/13027 , H01L2224/13028 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： 본 발명에서는 RDL 형성시 제 1 RDL이 형성된 영역을 적어도 하나의 제 2 RDL이 관통하여 지나가도록 함으로써, RDL 설계시 제약을 해소하고, 설계 자유도를 높일 수 있는 반도체 패키지 및 그 제조 방법이 개시된다.
일 예로, 다수의 본드 패드가 형성된 반도체 다이, 상기 반도체 다이의 상부에 형성되고, 그 일단부가 상기 본드 패드와 전기적으로 연결되는 제 1 RDL, 상기 제 1 RDL의 타단부를 관통하며, 상기 제 1 RDL과 전기적으로 절연되도록 형성된 적어도 하나의 제 2 RDL, 상기 제 1 RDL 및 제 2 RDL의 상부에 형성되고, 상기 제 1 RDL의 타단부를 노출시키는 패시베이션층 및 상기 패시베이션층의 상부에 형성되고, 노출된 상기 제 1 RDL의 타단부와 전기적으로 연결된 UBM을 포함하는 반도체 패키지가 개시된다.

98. 发明公开

KR1020140029872A 반도체 패키지 및 그 제조 방법 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：KR1020140029872A
公开(公告)日：2014-03-11
申请号：KR1020120095947
申请日：2012-08-30
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 박노선 , 유지연 , 정고운
IPC分类号： H01L23/488
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02123 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/02375 , H01L2224/0347 , H01L2224/0401 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05018 , H01L2224/05024 , H01L2224/05078 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05557 , H01L2224/05558 , H01L2224/05568 , H01L2224/05647 , H01L2224/06051 , H01L2224/06137 , H01L2224/10 , H01L2224/13027 , H01L2224/13028 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： The present invention discloses a semiconductor package capable of improving a design degree of freedom and solving the limitation of RDL design and a fabrication method thereof by enabling at least one second RDL to pass through an area where a first RDL is formed upon RDL formation. According to one embodiment of the present invention, the semiconductor package includes: a semiconductor die where a plurality of bond pads are formed, a first RDL which is formed in the upper part of the semiconductor die and includes one end part electrically connected to the bond pad, at least one second RDL which penetrates the other end part of the first RDL and is electrically insulated from the first RDL, a passivation layer which is formed on the upper part of the first RDL and the second RDL and exposes the other end part of the first RDL, and a UBM which is formed in the upper part of the passivation layer and is electrically connected to the other end part of the first RDL exposed.
摘要翻译：本发明公开了一种能够提高设计自由度和解决RDL设计限制的半导体封装及其制造方法，其特征在于，使得至少一个第二RDL通过在RDL形成时形成第一RDL的区域。根据本发明的一个实施例，半导体封装包括：形成多个接合焊盘的半导体管芯，形成在半导体管芯的上部的第一RDL，并且包括与该焊接部电连接的一个端部衬垫，穿过第一RDL的另一端部并且与第一RDL电绝缘的至少一个第二RDL，形成在第一RDL的上部上的钝化层和第二RDL，并露出另一端部的第一RDL，以及形成在钝化层的上部并与第一RDL的另一端电连接的UBM。

99. 发明公开

KR20180034671A 전도성 배리어 직접 하이브리드 접합 审中-公开
标题翻译：导电屏障直接混合连接
公开(公告)号：KR20180034671A
公开(公告)日：2018-04-04
申请号：KR20187007638
申请日：2016-08-25
IPC分类号： H01L21/18 , H01L21/52 , H01L23/00
CPC分类号： H01L24/09 , H01L21/50 , H01L24/03 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/036 , H01L2224/05005 , H01L2224/05078 , H01L2224/05082 , H01L2224/08145 , H01L2224/8019 , H01L2224/80895 , H01L2225/06513
摘要： 직접하이브리드접합을형성하는방법, 및하기를포함하는직접하이브리드접합으로부터생성된소자: 전도성배리어에의해캡핑되는, 바람직하게는소자또는회로에접속되는제1 세트의금속접합패드를갖고, 제1 기판상의금속접합패드에인접한제1 비금속영역을갖는제1 기판, 바람직하게는소자또는회로에접속된, 제1 세트의금속접합패드와정렬된, 제2 전도성배리어에의해캡핑된제2 세트의금속접합패드를갖고, 제2 기판상의금속접합패드에인접한제2 비금속영역을갖는제2 기판, 및제1 비금속영역을제2 비금속영역에접촉접합함으로써형성된전도성배리어에의해캡핑된제1 및제2 세트의금속접합패드사이의접촉-접합된계면.
摘要翻译：用于形成混合结直接方法，以及由直接混合结产生包括hagireul该设备：具有所述第一组的一个金属接合焊盘连接到优选的元件或电路，其通过导电阻挡封端，在第一基板上第一基板，优选的装置或一个，具有连接到电路的第一组的金属焊盘的对准，双金属接合所述第二组由具有第一非金属区的导电阻挡层，其邻近于所述金属接合焊盘封端的第一mitje第二组由第二基板封端的金属，mitje具有衬垫，所述第二基板与所述第二非金属区域粘接接触而形成的导电性阻挡上具有邻近金属接合焊盘的第二非金属区域第一非金属区域键合焊盘之间的接触键合界面。

100. 发明公开

KR1020160001033A 반도체 패키지 审中-实审
标题翻译：半导体封装
公开(公告)号：KR1020160001033A
公开(公告)日：2016-01-06
申请号：KR1020140078681
申请日：2014-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 정재홍
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L23/522 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05011 , H01L2224/05012 , H01L2224/05013 , H01L2224/05078 , H01L2224/05084 , H01L2224/05093 , H01L2224/05096 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05578 , H01L2224/0801 , H01L2224/08113 , H01L2224/08501 , H01L2224/08505 , H01L2224/13017 , H01L2224/13021 , H01L2224/13022 , H01L2224/13028 , H01L2224/16012 , H01L2224/16059 , H01L2224/16104 , H01L2224/48453 , H01L2224/48463 , H01L2924/00014 , H01L2924/00012 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599
摘要： 본발명은반도체패키지에관한것으로, 반도체소자와외부의핀을연결하는패드의구조를개선할수 있도록하는기술이다. 이러한본 발명은본딩패드로사용되는제 1금속층, 제 1금속층의상측에형성되며제 1금속층을기준으로하여양측으로분리되는제 2금속층, 제 2금속층의상측에형성되며제 금속층을기준으로하여양측으로분리되는제 3금속층, 및제 3금속층과제 2금속층을관통하여제 1금속층을노출시키며본딩볼이매립되는트렌치를포함한다.
摘要翻译：半导体封装技术领域本发明涉及一种改进将半导体部件与外部引脚连接的焊盘的结构的半导体封装和技术。根据本发明，半导体封装包括：用作焊盘的第一金属层; 第二金属层，形成在第一金属层的上侧，并且分隔成围绕第一金属层的两侧; 第三金属层，形成在所述第二金属层的上侧，并分离成围绕所述第一金属层的两侧; 以及沟槽，被配置为穿透所述第三和第二金属层以暴露所述第一金属层并且具有埋入其中的接合球。

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