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91. 发明授权

US08547756B2 Semiconductor memory device having an electrically floating body transistor 失效
公开(公告)号：US08547756B2
公开(公告)日：2013-10-01
申请号：US12897516
申请日：2010-10-04
申请人： Yuniarto Widjaja , Zvi Or-Bach
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： G11C7/00
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

92. 发明授权

US08120951B2 Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods 有权
标题翻译：存储器件，存储器件结构，结构，存储器件形成方法，电流传导器件和存储器单元编程方法
公开(公告)号：US08120951B2
公开(公告)日：2012-02-21
申请号：US12125797
申请日：2008-05-22
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： G11C11/36
CPC分类号： H01L27/2418 , G11C5/02 , G11C11/34 , G11C11/39 , G11C11/4026 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/003 , G11C2013/009 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2216/08 , H01L29/6609 , H01L45/00 , H01L45/141 , H01L45/145 , H01L45/16
摘要： Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
摘要翻译：一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管，电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

93. 发明申请

US20100296327A1 TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US20100296327A1
公开(公告)日：2010-11-25
申请号：US12785971
申请日：2010-05-24
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/00 , G11C11/4026 , G11C11/403 , G11C2211/4016 , H01L27/082 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定示例性实施例中，技术可以被实现为直接注入半导体存储器件，其包括连接到沿第一取向延伸的位线的第一区域和连接到沿第二取向延伸的源极线的第二区域。直接注入半导体存储器件还可以包括与在第二取向上延伸的字线间隔开并且电容耦合到字线的主体区域，其中主体区域电浮置并且设置在第一区域和第二区域之间。直接注入半导体存储器件还可以包括连接到沿着第二取向延伸的载流子注入管线的第三区域，其中第一区域，第二区域，体区域和第三区域以顺序连续的关系设置。

94. 发明授权

US07817466B2 Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells 有权
标题翻译：包括单元矩阵的半导体阵列和制造具有单元矩阵的半导体阵列的方法
公开(公告)号：US07817466B2
公开(公告)日：2010-10-19
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

95. 发明申请

US20090316492A1 MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING 有权
标题翻译：记忆细胞，记忆细胞阵列，使用方法和制备方法
公开(公告)号：US20090316492A1
公开(公告)日：2009-12-24
申请号：US12552903
申请日：2009-09-02
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C7/00 , H01L29/78 , H01L45/00 , H01L27/06 , H01L21/336 , G11C5/14
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
摘要翻译：提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

96. 发明申请

US20090086535A1 SEMICONDUCTOR ARRAY 有权
标题翻译：半导体阵列
公开(公告)号：US20090086535A1
公开(公告)日：2009-04-02
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

97. 发明申请

US20080251830A1 SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080251830A1
公开(公告)日：2008-10-16
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/102 , G11C16/04
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

98. 发明授权

US3686645A Charge storage flip-flop 失效
标题翻译：充电储存浮标
公开(公告)号：US3686645A
公开(公告)日：1972-08-22
申请号：US3686645D
申请日：1968-10-01
申请人： BELL TELEPHONE LABOR INC
发明人： BROJDO SAMUEL
IPC分类号： G11C11/40 , G11C11/402 , G11C11/411 , G11C13/04 , G11C11/42 , H03K3/286
CPC分类号： G11C11/4113 , G11C11/40 , G11C11/4026 , G11C11/4116 , G11C13/048
摘要： The invention uses nonlinear impedance elements connected to the pair of transistors in a flip-flop such that the base of each transistor is connected to a high impedance if the power supply voltage is removed. Inasmuch as the high impedance forces a slow decay of charge stored in the transistors, the state of the flipflop can be maintained by a pulsed power supply with a consequent reduction in average stand-by power. Further, using photosensitive transistors, photogenerated charge can be integrated and held. Advantageously, the apparatus is provided as an integrated circuit semiconductor memory array.

99. 发明授权

US3573499A Bipolar memory using stored charge 失效
标题翻译：双极存储器使用存储充电
公开(公告)号：US3573499A
公开(公告)日：1971-04-06
申请号：US3573499D
申请日：1969-05-02
申请人： BELL TELEPHONE LABOR INC
发明人： LYNES DENNIS J
IPC分类号： G11C11/402 , G11C11/411 , H03K3/012 , G11C11/40
CPC分类号： G11C11/4026 , G11C11/4113 , H03K3/012
摘要： A semiconductor memory characterized by simplified memory cells which operate on the charge storage phenomenon. Each cell comprises a pair of cross-coupled transistors, the collector electrodes of which are connected through separate diodes to a pair of information lines. Power is supplied in pulsed fashion via the information lines. No conventional load impedances are used. The coupling diodes prevent discharge of stored information during intervals in which no power is being supplied. The memory advantageously is embodied as a semiconductor integrated circuit.

100. 发明授权

US3564300A Pulse power data storage cell 失效
标题翻译：脉冲电源数据存储单元
公开(公告)号：US3564300A
公开(公告)日：1971-02-16
申请号：US3564300D
申请日：1968-03-06
申请人： IBM
发明人： HENLE ROBERT A
IPC分类号： G11C11/402 , G11C11/411 , G11C11/414 , H03K3/012 , H03K3/356 , H03K3/26
CPC分类号： G11C11/414 , G11C11/4026 , G11C11/4113 , G11C11/4116 , H03K3/012 , H03K3/356
摘要： A semiconductor storage cell for use in monolithic memories that perform storage and/or logic and storage functions. These cells each comprise a pair of semiconductor devices which are coupled together to form a bistable circuit. The bistable circuit is intermittently connected to a power supply in such a manner that the internal storage charge characteristics of the monolithic cell present a high-impedance discharge path when the power supply is in an off state. When the power supply is turned on the remaining voltage on the storage charge circuit is sufficient to insure that the monolithic memory cell attains its previous bistable state which existed prior to the power supply being turned off.

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