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91. 发明公开

EP1129553A2 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER 有权
标题翻译：作决定返回的方法和系统解码耦合
公开(公告)号：EP1129553A2
公开(公告)日：2001-09-05
申请号：EP99963877.8
申请日：1999-11-09
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar, E. , CREIGH, John, L. , HATAMIAN, Mehdi , KRUSE, David, E. , ABNOUS, Arthur , SAMUELI, Henry
IPC分类号： H04L25/14 , H04L1/00 , H04L25/06 , H04L25/497 , H04L25/03 , H04L25/49 , H04L7/02 , H04L7/033 , H04B3/23 , H04B3/52
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages: a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

92. 发明公开

EP1107013A2 A method and an apparatus for testing supply connections 有权
标题翻译： Verfahren und Vorrichtung zum Testen vonAnschlüssen
公开(公告)号：EP1107013A2
公开(公告)日：2001-06-13
申请号：EP00870209.4
申请日：2000-09-22
申请人： INTERUNIVERSITAIRE MICROELEKTRONICA CENTRUM VZW , Katholieke Hogeschool Brugge-Oostende
发明人： Manhaeve, Hans , Kerckenaere, Stefaan
IPC分类号： G01R31/316
CPC分类号： G01R31/2884 , G01R31/048 , G01R31/2818 , G01R31/3008 , G01R31/40
摘要： The invention presents an apparatus and method for testing supply connections (80) of an electronic device (10) by using a current mirror (20) configuration through using a particular connection of the branches of the current mirror to the supply line. Such connection results in unbalanced operation of the current mirror but depending whether said supply connection under test is proper or not, said unbalance is essentially different, resulting in a high sensitivity of the invented test device.
摘要翻译：本发明提出了一种用于通过使用电流镜（20）配置通过使用电流镜的分支到电源线的特定连接来测试电子设备（10）的电源连接（80）的装置和方法。这种连接导致电流镜的不平衡操作，但是根据所测试的供应连接是否适当，所述不平衡本质上是不同的，导致本发明测试装置的高灵敏度。

93. 发明公开

EP1085333A1 A method of testing an integrated circuit 有权
标题翻译： VERFAHREN ZUR RUHESTROMBESTIMMUNG
公开(公告)号：EP1085333A1
公开(公告)日：2001-03-21
申请号：EP99830581.7
申请日：1999-09-14
申请人： STMicroelectronics S.r.l.
发明人： Dallavalle, Carlo
IPC分类号： G01R31/30
CPC分类号： G01R31/3008 , G01R31/3004
摘要： A CMOS integrated circuit is tested by the following steps:

supplying the integrated circuit in static conditions,
biasing the p-type body regions (9) with a potential (VBBN) more negative than the negative pole (VSS) of the supply and the n-type body regions (12) with a potential (VBBP) more positive than the positive pole (VDD) of the supply,
setting a current threshold value (Ith),
measuring the current (IDDQ) absorbed,
comparing the current (IDDQ) measured with the threshold current (Ith),
accepting or rejecting the integrated circuit if the comparison shows that the current (IDDQ) measured is less than or is greater than the threshold value (Ith), respectively.
摘要翻译：通过以下步骤测试CMOS集成电路：将集成电路供给到静态条件下，用比电源的负极（VSS）更负的电位（VBBN）偏置p型体区域（9），并且n 具有比电源的正极（VDD）更正的电位（VBBP）的主体区域（12），设定电流阈值（Ith），测量吸收的电流（IDDQ），比较测量的电流（IDDQ）如果比较显示测量的电流（IDDQ）分别小于或大于阈值（Ith），则阈值电流（Ith），接受或拒绝集成电路。

94. 发明公开

EP0910799A2 IDDQ TESTABLE PROGRAMMABLE LOGIC ARRAYS AND A METHOD FOR TESTING SUCH A CIRCUIT 失效
标题翻译： IDDQ可测试的逻辑阵列可编程和可检验方法。这种电路
公开(公告)号：EP0910799A2
公开(公告)日：1999-04-28
申请号：EP98903233.0
申请日：1998-02-27
申请人： Koninklijke Philips Electronics N.V.
发明人： SACHDEV, Manoj
IPC分类号： G01R31 , G06F11 , H03K19
CPC分类号： G01R31/3008 , G01R31/3004 , G01R31/318516
摘要： The invention relates to an integrated circuit comprising a dynamic CMOS Progarmmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).

95. 发明公开

EP0838760A3 Multiple on-chip IDDQ monitors 失效
标题翻译： “多上的单芯片” IDDQ监测
公开(公告)号：EP0838760A3
公开(公告)日：1998-06-17
申请号：EP97307780.3
申请日：1997-10-02
申请人： Hewlett-Packard Company
发明人： Brown, Charles Allen
IPC分类号： G06F11/24 , G01R31/317
CPC分类号： G01R31/318577 , G01R31/3004 , G01R31/3008
摘要： In order to measure IDDQ in a large integrated circuit, multiple IDDQ monitors sampling the current drawn by selected portions of the circuit are placed on the integrated circuit chip. The output of each IDDQ monitor is combined and supplied to one output port (207) when any of the IDDQ monitors detect current in excess of a predetermined threshold. The output of each IDDQ monitor is also stored in a memory (209) for subsequent readout at a second output port (211) for detection of particular portions drawing the excessive current.

96. 发明公开

EP0664512A1 Design for testability technique of CMOS and BiCMOS ICs 失效
标题翻译： Verfahren zumprüfgerechtenEntwurf von CMOS和BICMOS IC。
公开(公告)号：EP0664512A1
公开(公告)日：1995-07-26
申请号：EP94830023.1
申请日：1994-01-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Penza Luigi , Favalli Michele , Ricco' Bruno
IPC分类号： G06F11/24
CPC分类号： G01R31/3008 , G01R31/3004 , G01R31/3012 , G01R31/31704
摘要： A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected BICSs avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional I DDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node ( shadow line ) and a supply rail of the IC.
摘要翻译：用于检测CMOS和BiCMOS逻辑IC中的桥接故障的DFT技术，采用由要测试的功能电路的信号节点驱动的专门集成的监控逆变器，用于显示临界值的中间电压的存在。监控逆变器通过专用阴影线提供，专用阴影线通过负载：用于静态实现的电阻或用于动态（时钟））实现的电阻连接到功能电路的任一个的电源轨。无串联连接的BICS避免了功能电路性能的恶化，并兼容缩减电源和在线测试技术。只有关键的桥接故障可以被可靠和有选择地检测，从而减少了拒绝的数量，不能进行常规的IDDQ测试。在修改的实施例中，本发明的DFT方案可以适于通过将某些监控逆变器的输出节点连接在一起以产生可测试的电流路径，从测试节点（阴影线）和供电轨 IC。

97. 发明公开

EP3089444A4 IMAGING UNIT AND IMAGING DEVICE 有权转让
标题翻译： BILDGEBUNGSEINHEIT和BILDGEBUNGSVORRICHTUNG
公开(公告)号：EP3089444A4
公开(公告)日：2017-07-12
申请号：EP14874390
申请日：2014-12-26
申请人： NIPPON KOGAKU KK
发明人： ARIMA HIROFUMI , SUGANUMA RYOICHI , MOTOORI RYUUZOU
IPC分类号： H04N5/225 , G01R31/30 , H04N5/232 , H04N5/357 , H04N5/361
CPC分类号： H01L27/14636 , G01R31/3008 , H01L27/14618 , H01L27/14629 , H01L2224/48091 , H01L2924/16195 , H04N5/2253 , H04N5/23241 , H04N5/23293 , H04N5/357 , H04N5/361 , H04N5/3698 , H01L2924/00014
摘要： An image-capturing unit includes: an image-capturing chip; a power supply circuit unit that outputs electrical power to be fed to the image-capturing chip; a power supply line that feeds electrical power from the power supply circuit unit to the image-capturing chip; a disconnecting unit that is provided to the power supply line and is electrically disconnecting the power supply circuit unit and the image-capturing chip when a leakage current of the image-capturing chip is measured; and an implementation substrate on which the power supply circuit unit, the image-capturing chip, the power supply line and the disconnecting unit are implemented.
摘要翻译：一种图像捕获单元包括：图像捕获芯片; 电源电路单元，其输出要被馈送到图像拍摄芯片的电力; 电源线，其从电源电路单元向摄像芯片供给电力; 断路单元，其设置于所述电源线，并且在测量所述图像拍摄芯片的漏电流时，将所述电源电路单元和所述图像拍摄芯片电断开; 以及在其上实现电源电路单元，图像拍摄芯片，电源线和断开单元的实现基板。

98. 发明公开

EP3089444A1 IMAGING UNIT AND IMAGING DEVICE 有权转让
标题翻译： BILDGEBUNGSEINHEIT UND BILDGEBUNGSVORRICHTUNG
公开(公告)号：EP3089444A1
公开(公告)日：2016-11-02
申请号：EP14874390.9
申请日：2014-12-26
申请人： Nikon Corporation
发明人： ARIMA, Hirofumi , SUGANUMA, Ryoichi , MOTOORI, Ryuuzou
IPC分类号： H04N5/369 , G03B17/00 , G03B17/02 , H01L27/14 , H04N5/225
CPC分类号： H01L27/14636 , G01R31/3008 , H01L27/14618 , H01L27/14629 , H01L2224/48091 , H01L2924/16195 , H04N5/2253 , H04N5/23241 , H04N5/23293 , H04N5/357 , H04N5/361 , H04N5/3698 , H01L2924/00014
摘要： An image-capturing unit includes: an image-capturing chip; a power supply circuit unit that outputs electrical power to be fed to the image-capturing chip; a power supply line that feeds electrical power from the power supply circuit unit to the image-capturing chip; a disconnecting unit that is provided to the power supply line and is electrically disconnecting the power supply circuit unit and the image-capturing chip when a leakage current of the image-capturing chip is measured; and an implementation substrate on which the power supply circuit unit, the image-capturing chip, the power supply line and the disconnecting unit are implemented.
摘要翻译：图像捕获单元包括：图像捕获芯片; 输出要馈送到图像捕获芯片的电力的电源电路单元; 电源线，其将来自所述电源电路单元的电力馈送到所述图像捕获芯片; 当测量图像捕获芯片的漏电流时，提供给电源线并断开电源电路单元和图像捕获芯片的断开单元; 以及其上实现了电源电路单元，图像捕获芯片，电源线和断开单元的实现基板。

99. 发明公开

EP2035979A4 EXHAUSTIVE DIAGNOSIS OF BRIDGING DEFECTS IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：桥接缺陷的集成电路中的综合诊断
公开(公告)号：EP2035979A4
公开(公告)日：2011-04-13
申请号：EP07798506
申请日：2007-06-13
申请人： IBM
发明人： HEABERLIN DOUGLAS C
IPC分类号： G01R31/30 , G01R31/28
CPC分类号： G01R31/2853 , G01R31/3008

100. 发明授权

EP2006698B1 Test apparatus and test method 有权
标题翻译：测试设备和测试程序
公开(公告)号：EP2006698B1
公开(公告)日：2010-03-24
申请号：EP08075805.5
申请日：2005-10-11
申请人： Advantest Corporation
发明人： Yasuo Furukawa, c/o Advantest Corporation
IPC分类号： G01R31/3187 , G01R31/30
CPC分类号： G01R31/3008

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