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91. 发明申请

US20170029272A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20170029272A1
公开(公告)日：2017-02-02
申请号：US15222006
申请日：2016-07-28
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： PENG REN
IPC分类号： B81C1/00 , H01L23/00 , H01L21/67 , H01L21/687 , H01L23/48 , H01L21/768
CPC分类号： B81C1/00801 , B81C2201/0154 , B81C2201/05 , B81C2203/0778 , H01L21/67063 , H01L21/6715 , H01L21/687 , H01L21/76861 , H01L21/76873 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/13 , H01L2224/02317 , H01L2224/02372 , H01L2224/02381 , H01L2224/13024
摘要： A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.
摘要翻译：一种制造半导体结构的方法包括：提供具有第一表面和第二表面的基底，其中在所述基底的第一表面上形成至少一个焊盘。该方法还包括形成至少一个通孔以通过从第二表面蚀刻衬底来暴露每个焊盘，形成晶种层以覆盖衬底的第二表面和每个通孔的侧壁和底表面，然后形成再分布金属层在形成在每个通孔的侧壁和底表面上的种子层的一部分上，以及围绕每个通孔的基板的第二表面。该方法还包括交替地执行预润湿处理和化学蚀刻工艺以完全去除未被再分布金属层覆盖的种子层的部分。

92. 发明申请

US20160043108A1 Semiconductor Structure with Multiple Active Layers in an SOI Wafer 审中-公开
标题翻译：半导体结构在SOI晶圆中具有多个有源层
公开(公告)号：US20160043108A1
公开(公告)日：2016-02-11
申请号：US14454262
申请日：2014-08-07
申请人： Silanna Semiconductor U.S.A., Inc.
发明人： Stephen A. Fanelli
IPC分类号： H01L27/12 , H01L21/84 , B81C3/00 , B81B7/00 , B81B7/02 , H01L21/762 , B81C1/00
CPC分类号： H01L27/1207 , B81C1/00238 , B81C1/00246 , B81C2203/0728 , B81C2203/0735 , B81C2203/0778 , B81C2203/0792 , H01L21/76251 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L27/1203 , H01L2224/73265 , H01L2924/13091
摘要： An semiconductor on insulator wafer has an insulator layer between a substrate layer and a semiconductor layer. A first active layer is formed in and on the semiconductor layer. A second active layer is formed in and on the substrate layer. In some embodiments, a handle wafer is bonded to the semiconductor on insulator wafer, and the substrate layer is thinned before forming the second active layer. In some embodiments, a third active layer may be formed in the substrate of the handle wafer. In some embodiments, the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other.
摘要翻译：绝缘体上半导体晶片在衬底层和半导体层之间具有绝缘体层。第一有源层形成在半导体层中和半导体层上。第二有源层形成在衬底层中和衬底层上。在一些实施例中，把手晶片结合到绝缘体上半导体晶片上，并且在形成第二有源层之前将衬底层变薄。在一些实施例中，可以在处理晶片的衬底中形成第三有源层。在一些实施例中，第一和第二有源层包括这些层之一中的MEMS器件和另一个中的CMOS器件。

93. 发明授权

US09202821B2 Thin-film transistors incorporated into three dimensional MEMS structures 有权
标题翻译：并入三维MEMS结构的薄膜晶体管
公开(公告)号：US09202821B2
公开(公告)日：2015-12-01
申请号：US14061415
申请日：2013-10-23
申请人： Pixtronix, Inc.
发明人： Patrick F. Brinkley , Wilhelmus A. De Groot , Jasper L. Steyn , Elif Selin Mungan
IPC分类号： H01L27/12 , H01L29/66 , H01L29/786 , B81C1/00 , G02B26/02
CPC分类号： H01L27/1218 , B81B2207/015 , B81C1/00246 , B81C2203/0742 , B81C2203/0778 , G02B26/023 , H01L27/1255 , H01L29/6675 , H01L29/78603 , H01L29/78642
摘要： This disclosure provides systems, methods and apparatus for forming electromechanical systems (EMS) displays where the area of a substrate occupied by a pixel circuit can be reduced if portions of the pixel circuit can be built in three dimensions. In some aspects, certain EMS displays can incorporate structures that are substantially normal to the surface of a substrate. Incorporating circuit components, such as transistors, into such structures, can reduce the area they occupy within the plane of the substrate. In some aspects, the components of a transistor can be fabricated directly into a MEMS anchor that supports a light modulator or a portion of an actuator over the substrate. In some other aspects, the transistor can be fabricated on one or more sidewalls of any MEMS structure.
摘要翻译：本公开提供了用于形成机电系统（EMS）显示器的系统，方法和装置，其中像素电路占据的基板的面积可以减小，如果像素电路的部分可以被构建在三维中。在一些方面，某些EMS显示器可以结合基本上垂直于基底表面的结构。将诸如晶体管的电路组件结合到这种结构中可以减少它们在衬底的平面内占据的面积。在一些方面，晶体管的部件可以直接制造成支撑光调制器或致动器的一部分在衬底上的MEMS锚。在一些其他方面，晶体管可以制造在任何MEMS结构的一个或多个侧壁上。

94. 发明授权

US09117932B2 Semiconductor pressure sensor and fabrication method thereof 有权
标题翻译：半导体压力传感器及其制造方法
公开(公告)号：US09117932B2
公开(公告)日：2015-08-25
申请号：US14027037
申请日：2013-09-13
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Kimitoshi Sato
IPC分类号： G01L9/00 , H01L21/00 , H01L29/84 , H01L27/06
CPC分类号： H01L29/84 , B81B2201/0264 , B81C1/00246 , B81C2203/0714 , B81C2203/0735 , B81C2203/0778 , G01L9/0042 , G01L9/0073 , H01L27/0617
摘要： At a pressure sensor region, a pressure sensor including a fixed electrode, a void and a movable electrode is formed. At a CMOS region, a memory cell transistor and a field effect transistor are formed. An etching hole communicating with the void is closed by a first sealing film. The void is formed by removing a region of a film identical to the film of a gate electrode of the memory cell transistor. The movable electrode is formed of a film identical to the film of a gate electrode.
摘要翻译：在压力传感器区域，形成包括固定电极，空隙和可动电极的压力传感器。在CMOS区域，形成存储单元晶体管和场效应晶体管。与空隙连通的蚀刻孔由第一密封膜封闭。通过去除与存储单元晶体管的栅电极的膜相同的膜的区域来形成空隙。可动电极由与栅电极的膜相同的膜形成。

95. 发明授权

US08897470B2 Method of fabricating integrated semiconductor device with MOS, NPN BJT, LDMOS, pre-amplifier and MEMS unit 有权
标题翻译：使用MOS，NPN BJT，LDMOS，前置放大器和MEMS单元制造集成半导体器件的方法
公开(公告)号：US08897470B2
公开(公告)日：2014-11-25
申请号：US12533055
申请日：2009-07-31
申请人： Hsueh-I Huang , Ming-Tung Lee , Shuo-Lun Tu
发明人： Hsueh-I Huang , Ming-Tung Lee , Shuo-Lun Tu
IPC分类号： H04R17/02 , B81C1/00
CPC分类号： B81C1/00246 , B81B2201/0257 , B81C1/0023 , B81C2203/0778
摘要： A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.
摘要翻译：一种制造集成半导体器件的方法，包括：提供具有第一区域和第二区域的衬底; 以及在所述第一区域上形成半导体单元，并且在一个工艺中在所述第二区域上形成微机电系统（MEMS）单元。

96. 再颁专利

USRE41889E1 Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced 有权
标题翻译：用于制造高灵敏度加速度和陀螺仪集成传感器的过程以及由此产生的传感器
公开(公告)号：USRE41889E1
公开(公告)日：2010-10-26
申请号：US10360367
申请日：2003-02-05
申请人： Paolo Ferrari , Benedetto Vigna , Pietro Montanini , Marco Ferrera
发明人： Paolo Ferrari , Benedetto Vigna , Pietro Montanini , Marco Ferrera
IPC分类号： H01L21/00
CPC分类号： H01L21/764 , B81B2201/0235 , B81B2201/0242 , B81C1/00246 , B81C2201/0109 , B81C2201/0177 , B81C2203/0735 , B81C2203/0778 , G01P15/0802 , G01P15/125 , G01P2015/0814 , H01L21/76202
摘要： A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.
摘要翻译：从外延层开始形成形成地震质量块的移动体，并且由具有高密度的钨的加权区域覆盖。为了制造质量，在衬底中形成掩埋的导电区域。然后，同时，在要形成可移动物体的区域中形成牺牲区域，并且在掩埋的导电区域上形成氧化物绝缘区域，以便部分地覆盖它们。然后使用核区域生长外延层。沉积和限定钨层，并且使用碳化硅层作为掩模，限定悬浮结构。最后，去除牺牲区域，形成气隙。

97. 发明申请

US20090134459A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090134459A1
公开(公告)日：2009-05-28
申请号：US12270463
申请日：2008-11-13
申请人： Yasushi GOTO , Tsukasa Fujimori , Heewon Jeong , Kiyoko Yamanaka
发明人： Yasushi GOTO , Tsukasa Fujimori , Heewon Jeong , Kiyoko Yamanaka
IPC分类号： H01L27/105 , H01L21/77
CPC分类号： B81C1/00246 , B81B2201/0235 , B81C2203/0728 , B81C2203/0735 , B81C2203/0778 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： As well as achieving both downsizing and thickness reduction and sensitivity improvement of a semiconductor device that has: a MEMS sensor formed by bulk micromachining technique such as an acceleration sensor and an angular rate sensor; and an LSI circuit, a packaging structure of the semiconductor device having the MEMS sensor and the LSI circuit can be simplified. An integrated circuit having MISFETs and wirings is formed on a silicon layer of an SOI substrate, and the MEMS sensor containing a structure inside is formed by processing a substrate layer of the SOI substrate. In other words, by using both surfaces of the SOI substrate, the integrated circuit and the MEMS sensor are mounted on one SOI substrate. The integrated circuit and the MEMS sensor are electrically connected to each other by a through-electrode provided in the SOI substrate.
摘要翻译：以及实现半导体器件的小型化和厚度降低以及灵敏度提高，其具有：通过体积微加工技术（例如加速度传感器和角速度传感器）形成的MEMS传感器; 并且LSI电路，可以简化具有MEMS传感器和LSI电路的半导体器件的封装结构。在SOI衬底的硅层上形成具有MISFET和布线的集成电路，并且通过处理SOI衬底的衬底层来形成包含内部结构的MEMS传感器。换句话说，通过使用SOI衬底的两个表面，集成电路和MEMS传感器安装在一个SOI衬底上。集成电路和MEMS传感器通过设置在SOI衬底中的通孔电连接。

98. 发明授权

US06960488B2 Method of fabricating a microfabricated high aspect ratio device with electrical isolation 有权
标题翻译：制造具有电气隔离的微细高宽比装置的方法
公开(公告)号：US06960488B2
公开(公告)日：2005-11-01
申请号：US09342348
申请日：1999-06-29
申请人： Timothy J. Brosnihan , James Bustillo , William A. Clark
发明人： Timothy J. Brosnihan , James Bustillo , William A. Clark
IPC分类号： B81B3/00 , B81B7/02 , G01C19/5719 , G01P15/08 , G01P15/097 , G01P15/10 , G01P15/125 , H01L21/00
CPC分类号： G01P15/097 , B81B2203/033 , B81C1/00246 , B81C2203/0778 , G01C19/5719 , G01P15/0802 , G01P15/0888 , G01P15/125 , G01P2015/0814
摘要： A microfabricated device having a high vertical aspect ratio and electrical isolation between a structure region and a circuit region. The device may be fabricated on a single substrate and may include electrical interconnections between the structure region and the circuit region. The device includes a substrate and an isolation trench surrounding a structure region in the substrate. The isolation trench includes a lining of a dielectric insulative material. A plurality of microstructure elements are located in the structure region and are laterally anchored to the isolation trench.
摘要翻译：一种微结构装置，其具有高垂直纵横比和结构区域与电路区域之间的电隔离。器件可以制造在单个衬底上，并且可以包括结构区域和电路区域之间的电互连。该器件包括衬底和围绕衬底中的结构区域的隔离沟槽。隔离沟槽包括介电绝缘材料的衬里。多个微结构元件位于结构区域中并横向锚定到隔离沟槽。

99. 发明授权

US06767751B2 Integrated driver process flow 有权
公开(公告)号：US06767751B2
公开(公告)日：2004-07-27
申请号：US10161191
申请日：2002-05-28
申请人： James A. Hunter
发明人： James A. Hunter
IPC分类号： H01L2100
CPC分类号： G02B26/0808 , B81B2201/045 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/016 , B81C2203/0735 , B81C2203/0778 , H01L27/0611
摘要： An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

100. 发明申请

US20030235932A1 INTEGRATED DRIVER PROCESS FLOW 有权
标题翻译：集成驱动程序流程
公开(公告)号：US20030235932A1
公开(公告)日：2003-12-25
申请号：US10161191
申请日：2002-05-28
申请人： Silicon Light Machines
发明人： James A. Hunter
IPC分类号： H01L021/00
CPC分类号： G02B26/0808 , B81B2201/045 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/016 , B81C2203/0735 , B81C2203/0778 , H01L27/0611
摘要： An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.
摘要翻译：包括一个或多个器件驱动器和单片耦合到所述一个或多个驱动器电路的衍射光调制器的集成器件。一个或多个驱动器电路被配置为处理接收到的控制信号并将经处理的控制信号传送到衍射光调制器。一种制造集成器件的方法优选包括制造用于多个晶体管中的每一个晶体管的前端部分，隔离多个晶体管的前端部分，制造衍射光调制器的前端部分，将前部衍射光调制器的端部，制造用于多个晶体管的互连，施加开放阵列掩模和湿蚀刻以访问衍射光调制器，以及制造衍射光调制器的后端部分，从而将衍射光调制器和多个晶体管。

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