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91. 发明授权

US09397104B2 SRAM cell and method for manufacturing the same 有权
标题翻译： SRAM单元及其制造方法
公开(公告)号：US09397104B2
公开(公告)日：2016-07-19
申请号：US13509891
申请日：2011-11-23
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L21/70 , H01L27/11 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1104 , H01L21/845 , H01L27/1211
摘要： In one embodiment, a SRAM cell may include a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may include a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may include a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may include a plurality of semiconductor sub-layers. The first and second fins can include different number of the semiconductor sub-layers and have different heights from each other.
摘要翻译：在一个实施例中，SRAM单元可以包括衬底和形成在衬底上的第一Fin场效应晶体管（FinFET）和第二FinFET。第一FinFET可以包括形成在衬底上的半导体层中，并与该半导体层相邻的第一鳍片，并且第二鳍片FET可以包括形成在半导体层中并邻接半导体层的第二鳍片。半导体层可以包括多个半导体子层。第一和第二散热片可以包括不同数量的半导体子层，并且彼此具有不同的高度。

92. 发明申请

US20160204199A1 MOSFET STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20160204199A1
公开(公告)日：2016-07-14
申请号：US14904871
申请日：2013-10-22
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou Yin
IPC分类号： H01L29/10 , H01L29/161 , H01L29/66 , H01L29/78 , H01L29/49 , H01L29/08 , H01L29/165
CPC分类号： H01L29/1033 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium channel layer (101), a dummy gate structure (200) and a sacrificial spacer (102); c. removing the silicon germanium channel layer and portions of the substrate which are not covered by the dummy gate structure (200) and located under both sides of the dummy gate structure 200, so as to form vacancies (201); d. selectively epitaxially growing a first semiconductor layer (300) on the semiconductor structure to fill bottom and sidewalls of the vacancies (201); and e. removing the sacrificial spacer (102) and filling a second semiconductor layer (400) in the vacancies which are not filled by the first semiconductor layer (300). In the semiconductor structure of the present disclosure, carrier mobility in the channel can be increased, negative effects induced by the short channel effects can be suppressed, and device performance can be enhanced.
摘要翻译：公开了一种MOSFET结构及其制造方法。该方法包括：a。提供衬底（100）; b。形成硅锗沟道层（101），伪栅极结构（200）和牺牲间隔物（102）; C。去除未被所述虚拟栅极结构（200）覆盖并位于所述虚拟栅极结构200的两侧的所述硅锗沟道层和所述衬底的部分，以形成空位（201）; d。在所述半导体结构上选择性地外延生长第一半导体层（300）以填充所述空位（201）的底部和侧壁; 和e。去除所述牺牲间隔物（102）并在未被所述第一半导体层（300）填充的空位中填充第二半导体层（400）。在本公开的半导体结构中，可以增加通道中的载流子迁移率，可以抑制由短通道效应引起的负面影响，并且可以提高器件性能。

93. 发明授权

US09379056B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09379056B2
公开(公告)日：2016-06-28
申请号：US14423020
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/311 , H01L21/3213 , H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L23/528 , H01L21/31111 , H01L21/32133 , H01L21/76802 , H01L21/76831 , H01L21/76838 , H01L21/76841 , H01L21/76877 , H01L21/76892 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：a）在衬底上形成金属互连衬垫; b）形成掩模层以覆盖金属互连衬里并在掩模层上形成露出金属互连衬套的开口; c）经由开口蚀刻和断开金属互连衬套，由此绝缘和隔离金属互连衬套。本发明还提供一种半导体结构，其包括衬底和金属互连衬套，其中金属互连衬里的端部通过在衬底内形成的绝缘壁而断开。本发明提供的结构和方法有利于缩短相邻金属互连衬套的端部之间的距离，节省器件面积并抑制金属互连衬套发生的短路。

94. 发明授权

US09373622B2 CMOS device with improved accuracy of threshold voltage adjustment and method for manufacturing the same 有权
标题翻译：具有提高阈值电压调整精度的CMOS器件及其制造方法
公开(公告)号：US09373622B2
公开(公告)日：2016-06-21
申请号：US14721386
申请日：2015-05-26
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huaxiang Yin , Hong Yang , Qingzhu Zhang , Qiuxia Xu
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L27/0924
摘要： An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.
摘要翻译： CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能。

95. 发明授权

US09350380B2 Sigma-delta modulator and analog-to-digital converter 有权
标题翻译： Σ-Δ调制器和模数转换器
公开(公告)号：US09350380B2
公开(公告)日：2016-05-24
申请号：US14425095
申请日：2013-02-28
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Lan Chen
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/324 , H03M1/002 , H03M3/38 , H03M3/424 , H03M3/438 , H03M3/50
摘要： A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator.
摘要翻译： Σ-Δ调制器和模数转换器。 Sigma-Delta调制器包括量化器，校正模块和RC积分器。校正模块包括产生校正水平的预定电阻。校正模块用于通过使用量化器中的比较器将校正电平与预定参考电压进行比较，以产生数字校正信号，基于该校正信号校正RC积分器中的电阻校正阵列中的电阻。预定电阻与RC积分器中的电阻校正阵列中的电阻相同。 Sigma-Delta调制器和模数转换器可以校正RC积分器中的电阻偏差。

96. 发明授权

US09349867B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09349867B2
公开(公告)日：2016-05-24
申请号：US14434437
申请日：2012-12-04
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Miao Xu , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/088 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/308 , H01L21/762 , H01L21/8234 , H01L29/06 , H01L29/10 , H01L29/161 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7851 , H01L21/02274 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/0257 , H01L21/26513 , H01L21/30604 , H01L21/308 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/1083 , H01L29/161 , H01L29/165 , H01L29/6681 , H01L29/7848
摘要： Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.
摘要翻译：提供半导体器件及其制造方法。示例性方法可以包括：在衬底上顺序地形成第一半导体层和第二半导体层; 图案化第二半导体层和第一半导体层以形成翅片; 在所述衬底上形成隔离层，其中所述隔离层暴露所述第一半导体层的一部分; 将离子注入翅片下面的基底的一部分，以形成穿通塞子; 形成跨越隔离层上的翅片的栅极堆叠; 以所述栅极叠层为掩模选择性蚀刻所述第二半导体层，以露出所述第一半导体层; 选择性地蚀刻第一半导体层，以在第二半导体层下面形成空隙; 以及在所述衬底上形成第三半导体层以形成源/漏区。

97. 发明授权

US09312361B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09312361B2
公开(公告)日：2016-04-12
申请号：US13578872
申请日：2012-05-18
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

98. 发明授权

US09306016B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09306016B2
公开(公告)日：2016-04-05
申请号：US14423395
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/00 , H01L29/00 , H01L29/417 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/78 , H01L29/165
CPC分类号： H01L29/41783 , H01L21/02181 , H01L21/02192 , H01L21/02194 , H01L21/30604 , H01L21/31111 , H01L21/31116 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/66825 , H01L29/7848 , H01L29/78654
摘要： The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device. The present invention is capable of eliminating pathway for leakage current between source/drain regions and SOI substrate at the meantime of reducing contact resistance at source/drain regions.
摘要翻译：本发明提供一种制造半导体器件的方法，其包括：提供SOI衬底，其包括基底层，位于基底层上的绝缘层和位于绝缘层上的有源层; 在SOI衬底上形成栅叠层; 用栅极叠层作为掩模蚀刻有源层，绝缘层和SOI衬底的基底层的一部分，以在栅叠层的两侧形成沟槽; 在所述沟槽内形成晶体介质层，其中所述晶体介质层的上表面低于所述绝缘层的上表面，并且不低于所述绝缘层的下表面; 并在晶体介质层上形成源/漏区。本发明还提供一种半导体器件。本发明能够消除源极/漏极区域和SOI衬底之间的泄漏电流的途径，同时降低源极/漏极区域的接触电阻。

99. 发明授权

US09306003B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09306003B2
公开(公告)日：2016-04-05
申请号：US14396709
申请日：2014-08-15
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Jing Xu , Jiang Yan , Bangming Chen , Hongli Wang , Bo Tang , Zhaoyun Tang , Yefeng Xu , Chunlong Li , Mengmeng Yang
IPC分类号： H01L29/06 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/306
CPC分类号： H01L29/0653 , H01L21/02236 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/76264 , H01L29/0649 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78654 , H01L29/78687 , H01L29/78696
摘要： A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.
摘要翻译：一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

100. 发明授权

US09263581B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09263581B2
公开(公告)日：2016-02-16
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/265 , H01L21/324 , H01L29/06
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

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