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91. 发明授权

US06697906B1 Semiconductor device supporting integrated data transfer bridging between CPU memory and I/O device 有权
标题翻译：半导体器件支持CPU内存和I / O设备之间的集成数据传输桥接
公开(公告)号：US06697906B1
公开(公告)日：2004-02-24
申请号：US09561340
申请日：2000-04-28
申请人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
发明人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
IPC分类号： G06F100
CPC分类号： G06F13/4031
摘要： A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.
摘要翻译：半导体器件连接到CPU，存储器和I / O设备以用作用于在存储器和I / O设备之间进行有效数据传输的数据传输桥。包括在桥芯片中的CPU接口和多个I / O接口通过内部总线连接到包括在桥芯片中的存储器接口。每个I / O接口都有一个读/写缓冲区和一个DMAC。包括在桥芯片中的仲裁器确定响应于从CPU接口和DMAC到存储器的数据传输的请求而允许数据传输的总线主机。当在存储器和I / O接口之间传输数据时，每个I / O接口都具有一个控制功能来跳过存储器中的一部分区域。

92. 发明授权

US06646651B1 Display controller 失效
标题翻译：显示控制器
公开(公告)号：US06646651B1
公开(公告)日：2003-11-11
申请号：US09596044
申请日：2000-06-16
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G09G502
CPC分类号： G09G5/36 , G09G5/363 , G09G5/39 , G09G5/397
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译：在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性通过将单位时钟分割成预定数量以高速功能和多功能显示。当从与显示帧相对应的刷新存储器输入或输出图像数据时，存储器内容和显示地址以1：n的比例被分配以并行地进行处理。结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示。所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

93. 发明授权

US06456268B1 Active matrix type liquid crystal display drive control apparatus 有权
标题翻译：有源矩阵型液晶显示驱动控制装置
公开(公告)号：US06456268B1
公开(公告)日：2002-09-24
申请号：US09609254
申请日：2000-06-30
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G3/3648 , G09G3/3655 , G09G2320/0204 , G09G2320/0219 , G09G2320/0247
摘要： By setting a gate voltage for each of the horizontal sync frequency bands, the flicker is reduced in a display mode of a low horizontal sync frequency. A drive control apparatus 10 includes: a frequency detection circuit 12 for detecting a horizontal sync frequency h; a gate-on voltage changing circuit 16 for changing a gate-on voltage Vg of a TFT 14 for liquid crystal drive, according to the horizontal sync frequency h detected by the frequency detection circuit 12; and a common voltage changing circuit 20 for changing a common voltage Vc of a liquid crystal 18 according to the horizontal sync frequency h detected by the frequency detection circuit 12.
摘要翻译：通过设置每个水平同步频带的栅极电压，在低水平同步频率的显示模式下，闪烁减小。驱动控制装置10包括：频率检测电路12，用于检测水平同步频率h; 根据由频率检测电路12检测的水平同步频率h，改变用于液晶驱动的TFT14的栅极导通电压Vg的栅极导通电压改变电路16; 以及用于根据由频率检测电路12检测的水平同步频率h改变液晶18的公共电压Vc的公共电压改变电路20。

94. 发明授权

US06428396B2 Method of producing a substrate for an information recording medium and method of producing an information recording medium 有权
标题翻译：一种信息记录介质用基板的制造方法及信息记录介质的制造方法
公开(公告)号：US06428396B2
公开(公告)日：2002-08-06
申请号：US09892854
申请日：2001-06-28
申请人： Hideki Isono , Hiroshi Takeda , Hisao Kawai
发明人： Hideki Isono , Hiroshi Takeda , Hisao Kawai
IPC分类号： B24B100
CPC分类号： G11B5/8404 , G11B5/82 , G11B23/502 , Y10S977/888
摘要： A method of producing a substrate for an information recording medium in which there is a step of washing and drying the substrate, which is also subjected to precision polishing. In the method, a correlation is preliminarily obtained between a contact angle of water on a surface of the substrate before the washing/drying step and a size (height) of protrusions attached to the surface of the substrate during the washing/drying step. The contact angle of water on the surface of the substrate before the washing/drying step is controlled so that the protrusions have a size (1) so as not to cause a hit when at least a recording layer is formed on the surface of the substrate and when a slider provided with a recording device and/or a reproducing device is made to run on a surface of the information recording medium, and (2) so as not to cause an error upon recording and/or reproducing the information recording medium.
摘要翻译：一种用于信息记录介质的基板的制造方法，其中还具有对进行精密抛光的基板进行清洗和干燥的步骤。在该方法中，在洗涤/干燥步骤之前，在基板的表面上的水的接触角与在洗涤/干燥步骤期间附着到基材的表面的突起的尺寸（高度）之间预先获得相关性。控制洗涤/干燥步骤之前的基板表面上的水的接触角，使得突起具有尺寸（1），以便在至少记录层形成在基板的表面上时不引起撞击并且当设置有记录装置和/或再现装置的滑块在信息记录介质的表面上运行时，以及（2）不会在记录和/或再现信息记录介质时引起错误。

95. 发明授权

US6094193A Display controller 失效
标题翻译：显示控制器
公开(公告)号：US6094193A
公开(公告)日：2000-07-25
申请号：US989390
申请日：1997-12-12
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/14 , G09G5/32 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/00 , G09G5/04
CPC分类号： G09G5/36 , G09G5/363 , G09G5/39 , G09G5/397
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunctional display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译：在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性通过将单位时钟分割成预定数量以高速功能和多功能显示。当从与显示帧相对应的刷新存储器输入或输出图像数据时，存储器内容和显示地址以1：n的比例被分配以并行地进行处理。结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示。所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

96. 发明授权

US6088743A Processor receiving response request corresponding to access clock signal with buffer for external transfer synchronous to response request and internal transfer synchronous to operational clock 有权
标题翻译：处理器接收响应请求，对应于访问时钟信号与缓冲器进行外部传输同步响应请求和内部传输同步到工作时钟
公开(公告)号：US6088743A
公开(公告)日：2000-07-11
申请号：US400997
申请日：1999-09-21
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F13/42 , G06F12/00 , G06F13/00 , G06F13/16 , G11C7/22 , G06F1/04 , G06F13/28 , G06F15/00
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
摘要翻译：存储器1响应于CPU 2的接收请求（200,201和202）与其中并入的自激振荡器102的振荡输出同步并且根据所述访问请求执行其内部操作，并且输出响应请求 103，用于与其内部操作同步地对所述CPU的所述访问请求。 CPU执行对存储器的访问请求，并且从外部获取数据或者响应于来自所访问的存储器的响应请求103并根据所述访问请求的种类而将数据输出到外部。

97. 发明授权

US5984737A Structure of connector housing 失效
标题翻译：连接器外壳结构
公开(公告)号：US5984737A
公开(公告)日：1999-11-16
申请号：US48781
申请日：1998-03-27
申请人： Toru Nagano , Hiroshi Takeda
发明人： Toru Nagano , Hiroshi Takeda
IPC分类号： H01R13/42 , H01R13/436 , H01R13/514
CPC分类号： H01R13/4367 , H01R13/4361
摘要： A housing body of a connector housing has a terminal receiving chamber receiving a connector terminal, a first terminal engagement portion engaging with the connector terminal received in the receiving chamber, a mounting portion to which a rear holder is mounted, and a holder engagement portion projecting within an insertion groove formed on the outer surface of the housing body. The rear holder has a second terminal engagement portion further engaging with the connector terminal engaged with the first terminal engagement portion in a state of being mounted to the mounting portion, a convex portion inserted into the insertion groove, and a engageable portion which projects from the convex portion and engages with the holder engagement portion. A mounting state of the rear holder can be securely maintained by engaging the holder engagement portion with the engageable portion within the insertion groove.
摘要翻译：连接器壳体的壳体具有容纳连接器端子的端子容纳室，与容纳在容纳室中的连接器端子接合的第一端子接合部分，安装有后保持器的安装部分和突出在形成在壳体的外表面上的插入槽内。后保持器具有第二端子接合部，该第二端子接合部在与安装部安装的状态下进一步与与第一端子接合部接合的连接器端子接合，插入插入槽的凸部和从该第二端子接合部突出的接合部凸起部分并与保持器接合部分接合。通过将保持器接合部与插入槽中的可接合部分接合，可以可靠地保持后保持器的安装状态。

98. 发明授权

US5706140A Optical distance measuring equipment 失效
标题翻译：光学距离测量设备
公开(公告)号：US5706140A
公开(公告)日：1998-01-06
申请号：US297543
申请日：1994-08-31
申请人： Jun Nishino , Hiroshi Takeda , Sigeru Ryugo , Hidefumi Ito , Takashi Yoshimura
发明人： Jun Nishino , Hiroshi Takeda , Sigeru Ryugo , Hidefumi Ito , Takashi Yoshimura
IPC分类号： G01S7/481 , G02B9/04
CPC分类号： G01S7/4811
摘要： An optical distance measuring equipment in which light from a light emission element is transmitted to an object through a light transmission lens, and light reflected on the object is received by a light reception element through a light reception lens so that a distance to the object is measured on the basis of light transmitting timing and light receiving timing. In the optical distance measuring equipment, a lens holding member for disposing the light transmission lens and the light reception lens substantially at the same distance relative to the light emission element and the light reception element respectively is provided in front of a light transmission/reception board on which the light emission element and the light reception element are installed.
摘要翻译：一种光学距离测量设备，其中来自发光元件的光通过透光透镜传输到物体，并且被物体反射的光被光接收元件通过光接收透镜接收，使得到物体的距离为基于光发射定时和光接收定时测量。在光学距离测量设备中，用于将光透射透镜和光接收透镜分别相对于发光元件和光接收元件分别设置在相同距离处的透镜保持部件设置在光发射/接收板其上安装有发光元件和光接收元件。

99. 发明授权

US5682563A Camera which displays information to a user corresponding to a message imprinted on film 失效
标题翻译：相机显示信息给与用户对应的消息印在电影上
公开(公告)号：US5682563A
公开(公告)日：1997-10-28
申请号：US604251
申请日：1996-02-21
申请人： Junichi Shinohara , Yoshimi Ohno , Takashi Hongou , Hiroshi Takeda , Keiji Himuro , Tatsutoshi Kitajima , Atsushi Satoh
发明人： Junichi Shinohara , Yoshimi Ohno , Takashi Hongou , Hiroshi Takeda , Keiji Himuro , Tatsutoshi Kitajima , Atsushi Satoh
IPC分类号： G03B17/18 , G03B17/24
CPC分类号： G03B17/24 , G03B17/18 , G03B2217/243
摘要： A camera which imprints alphanumeric messages on the film. The camera allows a user to view, in the order of most frequently used, the messages which can be imprinted. In order to reduce the cost of the camera, there is a dot matrix LCD display which can only display a limited number of characters which is less than the total number of characters of the largest message. After a user takes a picture, the dot matrix display scrolls through the message which has been imprinted on the film so that the user can confirm that the correct message has been imprinted. The speed at which the characters are scrolled or displayed is determined based on the total number of characters of the message. As an alternative to scrolling, the characters can be displayed one or two at a time. As an alternative, instead of displaying the alpha-numerical characters of the message, a graphical indication is given that some type of information has been imprinted on the film. The duration at which this confirmation of message imprinting is displayed or scrolled corresponds to the length of the message in order to give the user some indication of the message.
摘要翻译：在电影上印有字母数字消息的相机。相机允许用户以最常用的顺序查看可以打印的消息。为了降低相机的成本，有一个点阵LCD显示器，它只能显示少于最大消息的字符总数的有限数量的字符。用户拍摄照片后，点阵显示会滚动已经打印在胶片上的消息，以便用户可以确认正确的消息已经被打印。字符滚动或显示的速度是基于消息的总字符数确定的。作为滚动的替代方式，一次可以显示一个或两个字符。作为替代，代替显示消息的字母数字字符，给出了某种类型的信息已经印在电影上的图形指示。显示或滚动此消息打印确认的持续时间对应于消息的长度，以给予用户该消息的一些指示。

100. 发明授权

US5652858A Method for prefetching pointer-type data structure and information processing apparatus therefor 失效
标题翻译：用于预取指针型数据结构的方法及其信息处理装置
公开(公告)号：US5652858A
公开(公告)日：1997-07-29
申请号：US455335
申请日：1995-05-31
申请人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
发明人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/30043 , G06F12/0862 , G06F9/383 , G06F2212/1024 , G06F2212/6022 , G06F2212/6028
摘要： In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.
摘要翻译：为了允许指针型数据结构的预取，加载指令的指令字具有指示符提示，指示由指令加载的数据包括指定下一个数据的地址的指针。当CPU执行这样的指令，并且从主存储器加载由该指令请求的数据时，存储器接口电路中的预取电路使用该指针从主存储器读取包含由该指针指定的数据的块，然后临时存储在其中提供的预取缓冲器中。当CPU执行请求读取由该指针指定的数据的加载指令时，该存储块中的数据通过处理器接口电路和高速缓存控制电路提供给CPU。

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