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91. 发明申请

US20100084624A1 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US20100084624A1
公开(公告)日：2010-04-08
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh Fang Chen , Yen-Hao Shih , Ming Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh Fang Chen , Yen-Hao Shih , Ming Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

92. 发明申请

US20090279349A1 PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE 有权
标题翻译：在高电压状态下有两个或更多的大面积非晶区域的相变装置
公开(公告)号：US20090279349A1
公开(公告)日：2009-11-12
申请号：US12117164
申请日：2008-05-08
申请人： Yen-Hao Shih , Chieh Fang Chen , Hsiang-Lan Lung
发明人： Yen-Hao Shih , Chieh Fang Chen , Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： H01L45/126 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.
摘要翻译：这里描述了存储器件以及用于操作存储器件的方法。如本文所述的存储单元包括第一电极和第二电极。存储单元还包括具有沿第一和第二电极之间的电极间电流路径串联布置的第一和第二有源区的相变材料。

93. 发明授权

US07355897B2 Methods to resolve hard-to-erase condition in charge trapping non-volatile memory 有权
标题翻译：解决电荷捕获非易失性存储器中难擦除条件的方法
公开(公告)号：US07355897B2
公开(公告)日：2008-04-08
申请号：US11773857
申请日：2007-07-05
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.
摘要翻译：提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以随后的编程和擦除周期中的擦除条件。

94. 发明授权

US07242622B2 Methods to resolve hard-to-erase condition in charge trapping non-volatile memory 有权
标题翻译：解决电荷捕获非易失性存储器中难擦除条件的方法
公开(公告)号：US07242622B2
公开(公告)日：2007-07-10
申请号：US11359044
申请日：2006-02-22
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.
摘要翻译：提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以随后的编程和擦除周期中的擦除条件。

95. 发明申请

US20070133307A1 METHODS TO RESOLVE HARD-TO-ERASE CONDITION IN CHARGE TRAPPING NON-VOLATILE MEMORY 有权
公开(公告)号：US20070133307A1
公开(公告)日：2007-06-14
申请号：US11359044
申请日：2006-02-22
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

96. 发明申请

US20060131634A1 NON-VOLATILE MEMORY, NON-VOLATILE MEMORY CELL AND OPERATION THEREOF 审中-公开
标题翻译：非易失性存储器，非易失性存储器单元及其操作
公开(公告)号：US20060131634A1
公开(公告)日：2006-06-22
申请号：US10905194
申请日：2004-12-21
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： H01L21/8238 , H01L29/06
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792
摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.
摘要翻译：一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。电荷捕获层和控制栅极设置在衬底上。电介质层设置在基板，电荷俘获层和控制栅极之间。源极和漏极设置在电荷俘获层的每一侧上的衬底中。轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

97. 发明授权

US09082657B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09082657B2
公开(公告)日：2015-07-14
申请号：US13676672
申请日：2012-11-14
申请人： Chih-Wei Hu , Teng-Hao Yeh , Yen-Hao Shih
发明人： Chih-Wei Hu , Teng-Hao Yeh , Yen-Hao Shih
IPC分类号： H01L21/3205 , H01L27/115
CPC分类号： H01L27/11578 , H01L21/28575 , H01L27/11565 , H01L29/0891 , H01L29/2003 , H01L29/42316 , H01L29/42376 , H01L29/452 , H01L29/66462 , H01L29/7787
摘要： A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures.
摘要翻译：提供半导体结构及其制造方法。该方法包括以下步骤。半导体单元布置在基板上。在半导体单元上形成材料层。在半导体单元上形成第一图案化掩模层。第一图案化掩模层具有对应于半导体单元的一部分并且暴露材料层的掩模开口。去除由掩模开口暴露的材料层的一部分，以保留由掩模开口暴露的每个半导体单元的侧壁上的材料层的一部分，以形成间隔结构。

98. 发明授权

US09082656B2 NAND flash with non-trapping switch transistors 有权
标题翻译： NAND闪存与非陷阱开关晶体管
公开(公告)号：US09082656B2
公开(公告)日：2015-07-14
申请号：US13294852
申请日：2011-11-11
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

99. 发明授权

US08951862B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08951862B2
公开(公告)日：2015-02-10
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

100. 发明授权

US08634235B2 Phase change memory coding 有权
标题翻译：相变存储器编码
公开(公告)号：US08634235B2
公开(公告)日：2014-01-21
申请号：US12823508
申请日：2010-06-25
申请人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

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