专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20050018484A1 Nonvolatile semiconductor memory and programming method for the same 失效
标题翻译：非易失性半导体存储器和编程方法相同
公开(公告)号：US20050018484A1
公开(公告)日：2005-01-27
申请号：US10865937
申请日：2004-06-14
申请人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L27/10 , H01L29/78
CPC分类号： G11C16/10
摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.
摘要翻译：半导体存储器具有存储单元矩阵，其包括沿着行方向交替排列的多个第一和第二单元列，每个单元列由多个存储单元晶体管实现，并且外围电路被配置为驱动存储单元矩阵，从存储单元矩阵读取信息。外围电路包括（a）被配置为将第一数据写入第一单元列中的存储单元晶体管的引导程序电路，（b）滞后程序电路，被配置为将第二数据写入第一单元列之后的第二单元列中的存储单元晶体管写入数据，以及（c）被配置为控制第一单元列的存储单元晶体管的阈值电压的变化的电压控制器。

92. 发明授权

US06549464B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06549464B2
公开(公告)日：2003-04-15
申请号：US10187285
申请日：2002-07-02
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

93. 发明授权

US06459612B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06459612B2
公开(公告)日：2002-10-01
申请号：US09953687
申请日：2001-09-14
申请人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
发明人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3409
摘要： With a local self boost (LSB) technique, the distribution, of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.
摘要翻译：利用局部自升压（LSB）技术，将数据擦除后的阈值电压的分布设置为较高一侧，并且分布宽度在可读取单元擦除状态的范围内充分变窄。为此，在存储单元阵列上执行块写入。接下来，将预定电压设置为起始电压，对每个块执行软擦除。在执行擦除验证读取之后，将单元的阈值电压与确定基准值进行比较。作为该比较的结果，如果单元的阈值电压未达到确定基准值，则重复软擦除。在这种情况下，软擦除期间的预定电压从起始电压改变。当所有单元的阈值电压都达到确定基准值时，软擦除结束。

94. 发明授权

US06434055B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06434055B1
公开(公告)日：2002-08-13
申请号：US09767152
申请日：2001-01-23
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

95. 发明授权

US08711635B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08711635B2
公开(公告)日：2014-04-29
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译：非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压验证操作。

96. 发明授权

US08710573B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08710573B2
公开(公告)日：2014-04-29
申请号：US12831323
申请日：2010-07-07
申请人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
发明人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译：可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

97. 发明授权

US08520443B2 Nonvolatile semiconductor storage device and method for driving the same 失效
标题翻译：非易失性半导体存储装置及其驱动方法
公开(公告)号：US08520443B2
公开(公告)日：2013-08-27
申请号：US13238442
申请日：2011-09-21
申请人： Fumitaka Arai , Wataru Sakamoto
发明人： Fumitaka Arai , Wataru Sakamoto
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/06 , G11C16/3418
摘要： A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction, in which a first interval and a second interval wider than that are alternately repeated for intervals in the second direction between the memory cells. The storage device according to the embodiment comprises a drive unit for writing data in a first cell, then writing data in a second cell which is connected to the same word line as the first cell and is spaced at the first interval in the second direction, then reading the data in the second cell, and reading the data in the first cell with correction based on the read value of the second cell.
摘要翻译：根据一个实施例的存储装置包括在第一方向上串联连接并且通过排列的串联连接被布置成矩阵的存储单元，以及在垂直于第一方向的第二方向上连接存储单元的控制栅极的字线方向，其中对于在存储单元之间的第二方向上的间隔交替地重复比其宽的第一间隔和第二间隔。根据实施例的存储装置包括用于在第一单元中写入数据的驱动单元，然后在连接到与第一单元相同的字线并在第二方向上以第一间隔隔开的第二单元中写入数据，然后读取第二单元中的数据，并且基于第二单元的读取值来校正第一单元中的数据。

98. 发明申请

US20130010541A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130010541A1
公开(公告)日：2013-01-10
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

99. 发明申请

US20120025293A1 SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE AND A CONTROL GATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有浮动门和控制门的半导体存储器件及其制造方法
公开(公告)号：US20120025293A1
公开(公告)日：2012-02-02
申请号：US13194131
申请日：2011-07-29
申请人： Wataru Sakamoto , Fumitaka Arai
发明人： Wataru Sakamoto , Fumitaka Arai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval.
摘要翻译：根据一个实施例，提供了具有存储单元和字线的半导体存储器件。存储单元形成在半导体层中并且被布置成矩阵。每个存储单元具有浮动栅极和控制栅极。每个存储单元中的每一个在行方向串联连接。每个字线在列方向上连接到每个控制门。在列方向上交替地为存储单元提供第一和第二间隔。第二个间隔大于第一个间隔。

100. 发明申请

US20110272755A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110272755A1
公开(公告)日：2011-11-10
申请号：US13188803
申请日：2011-07-22
申请人： Masato ENDO , Fumitaka Arai
发明人： Masato ENDO , Fumitaka Arai
IPC分类号： H01L27/115
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate.
摘要翻译：一种半导体器件，包括设置在单元晶体管区域中的半导体衬底上的第一绝缘膜，设置在第一绝缘膜上的第一导电膜，设置在第一导电膜上的电极间绝缘膜，设置在第一绝缘膜上的第二导电膜电极间绝缘膜，在其上表面具有第一金属硅化物膜，形成在所述半导体基板的表面上的第一源极/漏极区域，设置在所述半导体基板上的选择栅极晶体管中的至少一个中的第二绝缘膜区域和周边晶体管区域，第三导电膜，设置在第二绝缘膜上，并且具有厚度小于其顶表面上的第一金属硅化物膜的厚度的第二金属硅化物膜，以及第二源极/漏极区域形成在半导体基板的表面上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式