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91. 发明授权

US07657799B2 Method and apparatus for testing a dual mode interface 有权
标题翻译：用于测试双模式接口的方法和装置
公开(公告)号：US07657799B2
公开(公告)日：2010-02-02
申请号：US11418401
申请日：2006-05-04
申请人： Yasser Ahmed , Robert Joseph Kapuschinsky , Ashok Khandelwal , Samuel Khoo , Lane A. Smith
发明人： Yasser Ahmed , Robert Joseph Kapuschinsky , Ashok Khandelwal , Samuel Khoo , Lane A. Smith
IPC分类号： G01R31/28
CPC分类号： G06F11/221
摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.
摘要翻译：公开了用于测试双模式接口的系统和方法。双模式接口包括第一选通电路和第二选通电路，其被配置为在接口的第一操作模式期间不可操作并且可在接口的第二操作模式期间操作。双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。

92. 发明授权

US07606302B2 Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权
标题翻译：在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置
公开(公告)号：US07606302B2
公开(公告)日：2009-10-20
申请号：US11541379
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译：提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。

93. 发明授权

US07560957B2 High-speed CML circuit design 有权
标题翻译：高速CML电路设计
公开(公告)号：US07560957B2
公开(公告)日：2009-07-14
申请号：US11421675
申请日：2006-06-01
申请人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/20 , H03K19/094
CPC分类号： H03K19/09432 , H03K19/01707
摘要： A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
摘要翻译：提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。负载耦合在电源节点和输出节点之间。负载包括耦合到输出节点的折叠有源电感器。

94. 发明授权

US07549074B2 Content deskewing for multichannel synchronization 有权
标题翻译：多通道同步的内容去歪斜
公开(公告)号：US07549074B2
公开(公告)日：2009-06-16
申请号：US11143370
申请日：2005-06-02
申请人： Ravikumar K. Charath , Vladimir Sindalovsky , Lane A. Smith
发明人： Ravikumar K. Charath , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G06F1/12
CPC分类号： H03M9/00 , H04J3/0632 , H04J3/0685
摘要： The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal. The data alignment signal is then read in all channels during the next read cycle, followed by subsequent reading of deskewed or otherwise synchronized data, such as for conversion of parallel data into serial data for subsequent data transmission.
摘要翻译：本发明的各种实施例提供了一种用于数据同步的多个数据信道之间的数据内容偏移校正的装置，系统和方法。各种实施例针对多个数据信道中的每个数据信道（诸如逗号字符）确定是否已经写入数据对准信号。当数据对准信号已被写入多个数据通道的数据通道时，这些实施例为具有数据对准信号的每个数据通道确定数据对准信号的相应通道位置。当多个数据信道的每个数据信道具有数据对准信号时，并且当在至少一个数据信道中在下一个读取周期读取数据对准信号时，各种实施例移动每个数据信道的相应读指针多个数据信道的数据对准信号的相应信道位置。然后在下一个读取周期期间在所有通道中读取数据对齐信号，随后读取去偏移或以其他方式同步的数据，例如用于将并行数据转换为串行数据以用于后续数据传输。

95. 发明授权

US07516226B2 Transmit adaptive equalization using ordered sets 有权
标题翻译：使用有序集发送自适应均衡
公开(公告)号：US07516226B2
公开(公告)日：2009-04-07
申请号：US10955997
申请日：2004-09-30
申请人： Ali U. Ahmed , Robert D. Brink , Lane A. Smith , Robert Snively
发明人： Ali U. Ahmed , Robert D. Brink , Lane A. Smith , Robert Snively
IPC分类号： G06F15/16
CPC分类号： H04B10/0779 , H04B10/07
摘要： In a communication system comprising first and second nodes, a transmit adaptive equalization technique is implemented utilizing ordered sets. The first and second nodes may communicate over a Fiber Channel link or other medium. The first and second nodes comprise respective transmitter and receiver pairs, with the transmitter of the first node configured for communication with the receiver of the second node and the receiver of the first node configured for communication with the transmitter of the second node. The first node is operative to receive from the second node information specifying an adjustment to one or more equalization parameters of the first node. The information is received in designated portions of one or more ordered sets transmitted from the second node to the first node in conjunction with initialization of a communication link between the first and second nodes. The first node adjusts the equalization parameter(s) in accordance with the received information.
摘要翻译：在包括第一和第二节点的通信系统中，利用有序集来实现发射自适应均衡技术。第一和第二节点可以通过光纤通道链路或其他介质进行通信。第一和第二节点包括相应的发射机和接收机对，其中第一节点的发射机被配置用于与第二节点的接收机进行通信，并且第一节点的接收机被配置用于与第二节点的发射机进行通信。第一节点可操作以从第二节点接收指定对第一节点的一个或多个均衡参数的调整的信息。结合第一和第二节点之间的通信链路的初始化，在从第二节点发送到第一节点的一个或多个有序集合的指定部分中接收信息。第一节点根据接收到的信息调整均衡参数。

96. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

97. 发明申请

US20080225734A1 METHOD AND APPARATUS FOR DATA RATE DETECTION USING A DATA EYE MONITOR 有权
标题翻译：使用数据眼监视器进行数据速率检测的方法和装置
公开(公告)号：US20080225734A1
公开(公告)日：2008-09-18
申请号：US11686144
申请日：2007-03-14
申请人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04J1/16
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译：提供了使用数据眼监视器进行数据速率检测的方法和装置。数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。

98. 发明申请

US20080191789A1 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US20080191789A1
公开(公告)日：2008-08-14
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

99. 发明授权

US07312667B2 Statically controlled clock source generator for VCDL clock phase trimming 失效
标题翻译：用于VCDL时钟相位修整的静态时钟源发生器
公开(公告)号：US07312667B2
公开(公告)日：2007-12-25
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03B27/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.
摘要翻译：本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。在这个修整过程中，对这些输出时钟的静态变化进行调整。本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

100. 发明授权

US07212048B2 Multiple phase detection for delay loops 有权
标题翻译：延迟环路的多相检测
公开(公告)号：US07212048B2
公开(公告)日：2007-05-01
申请号：US11138703
申请日：2005-05-26
申请人： Peter C. Metz , Vladimir Sindalovsky , Lane A. Smith
发明人： Peter C. Metz , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/087 , H03L7/097 , H03L7/0998 , H04L7/033
摘要： A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.
摘要翻译：电路（例如，接收器）具有延迟环路（例如，电压控制的延迟环路）和至少两个相位检测器（PD），其中每个PD比较由延迟环路产生的不同的时钟信号对。然后使用不同PD的输出来产生用于调整由延迟环路中的延迟元件提供的延迟的控制信号。在一个实现中，控制信号指示仅当两个PD同意该调整时才应进行延迟调整。这种多PD技术可以减少由延迟环使用的参考时钟信号中的非50％占空比产生其多个时钟信号的抖动。

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