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91. 发明申请

US20050055704A1 Device of DISC-rejection pin 审中-公开
标题翻译： DISC拒绝引脚的设备
公开(公告)号：US20050055704A1
公开(公告)日：2005-03-10
申请号：US10930744
申请日：2004-09-01
申请人： Jung Lee
发明人： Jung Lee
IPC分类号： G11B33/02
CPC分类号： G11B33/022
摘要： A device of DISC-rejection-pin placed on the DISC drive, includes a holding device and a pin, wherein the holding device is comprised of two sets of extrusion, and each set of extrusion has two (upper and lower) circular extruding portions, the space between which is smaller than the diameter of the pin, and an appropriate distance between the two sets of extruding portion is smaller than the length of the pin, and the pin is held by the two sets of extruding portion.
摘要翻译：放置在DISC驱动器上的DISC排斥针的装置包括保持装置和销，其中保持装置由两组挤出组成，每组挤出具有两个（上下）圆形挤出部分，其间距小于销的直径，并且两组挤出部之间的适当距离小于销的长度，并且销由两组挤出部保持。

92. 发明申请

US20050047530A1 Method and arrangement for detecting a random access channel preamble using multiple antenna reception in a communication system 有权
标题翻译：用于在通信系统中使用多个天线接收来检测随机接入信道前同步码的方法和装置
公开(公告)号：US20050047530A1
公开(公告)日：2005-03-03
申请号：US10651200
申请日：2003-08-29
申请人： Jung Lee , Anil Rao
发明人： Jung Lee , Anil Rao
IPC分类号： H04B7/005 , H04B7/08 , H04L1/06 , H04L1/02
CPC分类号： H04B7/086 , H04L1/0618 , H04W52/50
摘要： In a method and arrangement for detecting a random access channel preamble in a received uplink signal, the uplink signal is received at one or more receive antennas and contains data related to a random access channel preamble. The received uplink signal is subjected to spatial processing and temporal processing in order to detect the random access channel preamble. A best cell portion for communicating with a user may also be determined based on the detected preamble. The best cell portion represents a portion of a cell where a received uplink signal from a user has a highest signal to interference ratio. The detected random access channel preamble is indicative of the best cell portion for communicating with the user.
摘要翻译：在用于检测接收到的上行链路信号中的随机接入信道前同步码的方法和装置中，在一个或多个接收天线处接收上行链路信号，并且包含与随机接入信道前导码有关的数据。接收到的上行链路信号经受空间处理和时间处理，以便检测随机接入信道前同步码。还可以基于检测到的前导码来确定用于与用户通信的最佳小区部分。最好的小区部分表示从用户接收的上行链路信号具有最高的信号与干扰比的小区的一部分。检测到的随机接入信道前导码指示用于与用户通信的最佳小区部分。

93. 发明申请

US20120098109A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20120098109A1
公开(公告)日：2012-04-26
申请号：US13315039
申请日：2011-12-08
申请人： Dongkyun Ko , Jung Lee , Jaesun An
发明人： Dongkyun Ko , Jung Lee , Jaesun An
IPC分类号： H01L23/552 , H01L21/56
CPC分类号： H01L21/78 , H01L21/561 , H01L23/3121 , H01L23/552 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H05K1/0218 , H05K3/0032 , H05K3/0052 , H05K3/284 , H05K2203/0415 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
摘要翻译：提供一种芯片封装，其包括具有多个用于更好的电磁干扰屏蔽的导电连接器的屏蔽层。导电连接器可以灵活地布置在模塑料中，以更好的屏蔽性能。具有导电连接器的屏蔽层用作EMI屏蔽，屏蔽层在封装结构内电接地。

94. 发明授权

US07975164B2 DDR memory controller 有权
标题翻译： DDR内存控制器
公开(公告)号：US07975164B2
公开(公告)日：2011-07-05
申请号：US12157081
申请日：2008-06-06
申请人： Jung Lee , Mahesh Gopalan
发明人： Jung Lee , Mahesh Gopalan
IPC分类号： G06F1/04 , G06F1/12 , G06F12/00 , H03K19/173 , H03K19/00 , G11C7/00 , G11C8/00 , G11C29/00 , G01R35/00 , G01R31/00 , G01R31/28 , G01B5/02
CPC分类号： G06F13/4243 , G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.
摘要翻译：描述了DDR存储器控制器，其中通过可编程地延迟存储器控制器的核心时钟来创建核心域捕获时钟。在系统环境中与DDR存储器一致地在初始化序列上电期间校准该捕获时钟的延迟，从而最小化系统延迟的影响并增加设备和系统产量。另外的实施例还包括可编程地延迟输入的dq信号。

95. 发明申请

US20100110656A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：芯片包装及其制造方法
公开(公告)号：US20100110656A1
公开(公告)日：2010-05-06
申请号：US12388771
申请日：2009-02-19
申请人： Dongkyun Ko , Jung Lee , Jaesun An
发明人： Dongkyun Ko , Jung Lee , Jaesun An
IPC分类号： H05K9/00 , B29D31/00
CPC分类号： H01L21/78 , H01L21/561 , H01L23/3121 , H01L23/552 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H05K1/0218 , H05K3/0032 , H05K3/0052 , H05K3/284 , H05K2203/0415 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A chip package including a plurality of conductive bodies and a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer over the molding compound contacts with the conductive bodies disposed on the substrate, and the shielding layer and the conductive bodies function as EMI shield. The shielding layer is electrically grounded through the conductive bodies connected to the laminate substrate and the ground plane of the substrate.
摘要翻译：提供了包括多个导电体和用于更好的电磁干扰屏蔽的屏蔽层的芯片封装。模制化合物上的屏蔽层与设置在基板上的导电体接触，并且屏蔽层和导电体用作EMI屏蔽。屏蔽层通过连接到层叠基板的导电体和基板的接地平面进行电接地。

96. 发明申请

US20100109132A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20100109132A1
公开(公告)日：2010-05-06
申请号：US12414996
申请日：2009-03-31
申请人： Dongkyun Ko , Jung Lee , Jaesun An
发明人： Dongkyun Ko , Jung Lee , Jaesun An
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L21/78 , H01L21/561 , H01L23/3121 , H01L23/552 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H05K1/0218 , H05K3/0032 , H05K3/0052 , H05K3/284 , H05K2203/0415 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
摘要翻译：提供一种芯片封装，其包括具有多个用于更好的电磁干扰屏蔽的导电连接器的屏蔽层。导电连接器可以灵活地布置在模塑料中，以更好的屏蔽性能。具有导电连接器的屏蔽层用作EMI屏蔽，屏蔽层在封装结构内电接地。

97. 发明申请

US20090307521A1 DDR memory controller 有权
标题翻译： DDR内存控制器
公开(公告)号：US20090307521A1
公开(公告)日：2009-12-10
申请号：US12157081
申请日：2008-06-06
申请人： Jung Lee , Mahesh Gopalan
发明人： Jung Lee , Mahesh Gopalan
IPC分类号： G06F1/04 , G06F12/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.
摘要翻译：描述了DDR存储器控制器，其中通过可编程地延迟存储器控制器的核心时钟来创建核心域捕获时钟。在系统环境中与DDR存储器一致地在初始化序列上电期间校准该捕获时钟的延迟，从而最小化系统延迟的影响并增加设备和系统产量。另外的实施例还包括可编程地延迟输入的dq信号。

98. 发明申请

US20080076429A1 SYSTEM FOR CONTROL, MANAGEMENT, AND TRANSMISSION FOR SOFT HANDOFF IN AN OFDMA-BASED COMMUNICATION SYSTEM 审中-公开
标题翻译：用于基于通信系统的软交换的控制，管理和传输系统
公开(公告)号：US20080076429A1
公开(公告)日：2008-03-27
申请号：US11851845
申请日：2007-09-07
申请人： David Comstock , Jianmin Lu , Anthony Soong , Zhigang Rong , Jung Lee
发明人： David Comstock , Jianmin Lu , Anthony Soong , Zhigang Rong , Jung Lee
IPC分类号： H04Q7/20
CPC分类号： H04W36/18
摘要： A versatile system for controlling and managing resources for Soft Handoff Group operations is disclosed. The system determines which of a plurality of sectors in an access network is a serving sector for an access terminal. An active set of the plurality of sectors is assigned to the access terminal, comprising the serving sector. A soft handoff set for the access terminal is identified from the active set. A soft handoff group for the access terminal is identified from the soft handoff set. The access terminal's transmissions within the access network are managed according to the identified soft handoff group.
摘要翻译：公开了一种用于软切换组操作的控制和管理资源的通用系统。系统确定接入网络中的多个扇区中的哪一个是用于接入终端的服务扇区。多个扇区的活动集被分配给包括服务扇区的接入终端。从活动集中识别接入终端的软越区切换。从软切换集中识别接入终端的软切换组。根据所识别的软切换组来管理接入终端在接入网内的传输。

99. 发明申请

US20080030969A1 Method for manufacturing a printed circuit board with a thin film capacitor embedded therein having a dielectric film by using laser lift-off, and printed circuit board with a thin film capacitor embedded therein manufactured thereby 有权
标题翻译：制造具有通过使用激光剥离的具有电介质膜的薄膜电容器的印刷电路板的制造方法以及由此制造的具有嵌入其中的薄膜电容器的印刷电路板
公开(公告)号：US20080030969A1
公开(公告)日：2008-02-07
申请号：US11808298
申请日：2007-06-08
申请人： Jung Lee , Yul Chung , In Hyung Lee
发明人： Jung Lee , Yul Chung , In Hyung Lee
IPC分类号： H05K7/02 , H01L21/62
CPC分类号： H05K1/162 , H01G4/33 , H01G13/00 , H01L21/4857 , H01L23/50 , H01L2924/0002 , H05K2201/0108 , H05K2201/0175 , H05K2201/0179 , H05K2203/016 , H05K2203/107 , Y10T29/43 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
摘要翻译：一种制造其中嵌有电容器的印刷电路板的方法，其中具有使用激光剥离的电介质膜，以及由此制造的电容器。在该方法中，在透明基板上形成电介质膜并进行热处理。在热处理电介质膜上形成第一导电层。将激光束照射到从透明基板的下方形成的堆叠上，以将透明基板与堆叠分离。在将透明基板与堆叠体分离之后，在电介质膜上形成具有预定图案的第二导电层。此外，绝缘层和第三导电层形成在第一和第二导电层上，以预定数量相互交替。

100. 发明申请

US20070136615A1 System and method for reducing power used to execute application program 审中-公开
标题翻译：用于降低用于执行应用程序的功率的系统和方法
公开(公告)号：US20070136615A1
公开(公告)日：2007-06-14
申请号：US11635203
申请日：2006-12-07
申请人： Donghwan Son , Jung Lee , Hyung Lee
发明人： Donghwan Son , Jung Lee , Hyung Lee
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： Provided is a system and method of controlling power, the system and method capable of predicting optimal speeds of operation clocks of a central processing unit (CPU) and a memory used to execute an application program, thereby reducing power used to execute the application program. The system for controlling power includes a requirement prediction module predicting a requirement of central processing unit (CPU) performance and a requirement of memory usage for executing the application program; an operation clock determining unit determining optimal speeds of operation clocks of the CPU and the memory for executing the application program based on the requirements; and a clock speed/driving voltage generating unit generating optimal speeds of the operation clocks and optimal driving voltages of the CPU and the memory for executing the application program based on the determined optimal speeds of the operation clocks.
摘要翻译：提供了一种控制功率的系统和方法，能够预测中央处理单元（CPU）的操作时钟的最佳速度和用于执行应用程序的存储器的系统和方法，从而减少用于执行应用程序的功率。用于控制功率的系统包括：预测中央处理单元（CPU）性能要求的预测模块和执行应用程序的存储器使用需求; 操作时钟确定单元，用于根据需要确定CPU和用于执行应用程序的存储器的操作时钟的最佳速度; 以及时钟速度/驱动电压产生单元，其基于所确定的操作时钟的最佳速度，生成CPU和用于执行应用程序的存储器的操作时钟的最佳速度和最佳驱动电压。

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