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91. 发明授权

US08299546B2 Semiconductor devices with vertical extensions for lateral scaling 有权
标题翻译：具有横向缩放垂直延伸的半导体器件
公开(公告)号：US08299546B2
公开(公告)日：2012-10-30
申请号：US12731481
申请日：2010-03-25
申请人： Zhibin Ren , Kevin K. Chan , Chung-Hsun Lin , Xinhui Wang
发明人： Zhibin Ren , Kevin K. Chan , Chung-Hsun Lin , Xinhui Wang
IPC分类号： H01L21/86 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L27/1203 , H01L29/41783 , H01L29/66628
摘要： A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法，其中延伸区域以垂直取向形成在衬底上。在一个实施例中，该方法包括提供掺杂有第一导电掺杂剂的半导体衬底。凸起的延伸区域形成在由半导体衬底的第二部分分离的半导体衬底的第一部分上。凸起的延伸区域具有第二导电掺杂剂的第一浓度。凸起的源极区域和凸起的漏极区域形成在凸起的延伸区域上。升高的源极区域和升高的漏极区域各自具有第二导电掺杂剂的第二浓度，其中第二浓度大于第一浓度。栅极结构形成在半导体衬底的第二部分上。

92. 发明授权

US08138547B2 MOSFET on silicon-on-insulator REDX with asymmetric source-drain contacts 有权
标题翻译： MOSFET上绝缘体上的REDX具有不对称的源极 - 漏极触点
公开(公告)号：US08138547B2
公开(公告)日：2012-03-20
申请号：US12548005
申请日：2009-08-26
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L29/41733 , H01L29/458 , H01L29/66772 , H01L29/7839 , H01L29/78624
摘要： A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.
摘要翻译：公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。在半导体层中形成源延伸和漏扩展区。在半导体层中形成深漏极区域和深源极区域。第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触并且栅极屏蔽金属沉积物抵靠深漏极区域。在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

93. 发明授权

US08138030B2 Asymmetric finFET device with improved parasitic resistance and capacitance 有权
标题翻译：具有改善的寄生电阻和电容的非对称finFET器件
公开(公告)号：US08138030B2
公开(公告)日：2012-03-20
申请号：US12559996
申请日：2009-09-15
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/66795
摘要： A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region.
摘要翻译：一种用于形成鳍状场效应晶体管（finFET）器件的方法包括：在衬底中形成翅片结构，形成垂直于翅片结构的栅极堆叠结构，并以一定角度（...）将离子注入到衬底中以形成源极区域和漏极区域，其中角度（θ）相对于源极区域是倾斜的。

94. 发明申请

US20120043585A1 Field Effect Transistor Device with Shaped Conduction Channel 有权
公开(公告)号：US20120043585A1
公开(公告)日：2012-02-23
申请号：US12860977
申请日：2010-08-23
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/335 , H01L29/772
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

95. 发明申请

US20120007183A1 Multi-gate Transistor Having Sidewall Contacts 有权
标题翻译：具有侧壁触点的多栅极晶体管
公开(公告)号：US20120007183A1
公开(公告)日：2012-01-12
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

96. 发明申请

US20110309448A1 DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL 有权
标题翻译： SRAM单元的多栅极晶体管的不同接触的接触
公开(公告)号：US20110309448A1
公开(公告)日：2011-12-22
申请号：US12816825
申请日：2010-06-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A complementary metal-oxide-semiconductor static random access memory cell that includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.
摘要翻译：具有多个P沟道多栅极晶体管和多个N沟道多栅极晶体管的互补金属氧化物半导体静态随机存取存储单元。每个晶体管包括栅电极和由至少一个栅极电极隔开的源极和漏极区域。 SRAM单元还包括形成在至少一个晶体管的源区和漏区内的多个触点。至少一个晶体管的多个触点凹入预定的凹陷量，其中至少一个晶体管的电阻基于预定的凹陷量而变化。

97. 发明申请

US20110233688A1 NOVEL DEVICES WITH VERTICAL EXTENSIONS FOR LATERAL SCALING 有权
标题翻译：具有垂直延伸的垂直延伸的新颖设备
公开(公告)号：US20110233688A1
公开(公告)日：2011-09-29
申请号：US12731481
申请日：2010-03-25
申请人： Zhibin Ren , Kevin K. Chan , Chung-Hsun Lin , Xinhui Wang
发明人： Zhibin Ren , Kevin K. Chan , Chung-Hsun Lin , Xinhui Wang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L27/1203 , H01L29/41783 , H01L29/66628
摘要： A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法，其中延伸区域以垂直取向形成在衬底上。在一个实施例中，该方法包括提供掺杂有第一导电掺杂剂的半导体衬底。凸起的延伸区域形成在由半导体衬底的第二部分分离的半导体衬底的第一部分上。凸起的延伸区域具有第二导电掺杂剂的第一浓度。凸起的源极区域和凸起的漏极区域形成在凸起的延伸区域上。升高的源极区域和升高的漏极区域各自具有第二导电掺杂剂的第二浓度，其中第二浓度大于第一浓度。栅极结构形成在半导体衬底的第二部分上。

98. 发明申请

US20110108900A1 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR 有权
标题翻译：双向自对准FET电容器
公开(公告)号：US20110108900A1
公开(公告)日：2011-05-12
申请号：US12616861
申请日：2009-11-12
申请人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

99. 发明授权

US09068936B2 Graphene sensor 有权
公开(公告)号：US09068936B2
公开(公告)日：2015-06-30
申请号：US13605107
申请日：2012-09-06
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/786 , H01L21/336 , G01N27/414 , H01L29/423 , H01L29/49 , H01L29/66
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78684 , H01L51/0048
摘要： A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

100. 发明授权

US08835997B2 Low extension dose implants in SRAM fabrication 有权
标题翻译： SRAM制造中的低延伸剂量植入物
公开(公告)号：US08835997B2
公开(公告)日：2014-09-16
申请号：US13464267
申请日：2012-05-04
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.
摘要翻译：静态随机存取存储器制造阵列包括至少一个p型场效应晶体管，其包括栅极堆叠和形成具有栅极长度L gate和有效栅极长度的栅极的隔离间隔，Leff以及与栅极堆叠相邻的源极和漏极区域其中源极和漏极区域由低延伸剂量植入物形成，其降低了Lgate和Leff之间的差异。

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