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91. 发明申请

US20060134866A1 NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060134866A1
公开(公告)日：2006-06-22
申请号：US11018507
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.
摘要翻译：提供非易失性存储器。存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。其中介电层设置在基板上。导电层设置在电介质层上。隔离层设置在基板上并且邻近电介质层和导电层。掩埋位线设置在衬底中并在隔离层下方。隧道电介质层设置在导电层和隔离层的基板和侧壁上。电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。字线设置在基板上，与埋入位线交叉。

92. 发明授权

US09196315B2 Three dimensional gate structures with horizontal extensions 有权
标题翻译：具有水平延伸的三维门结构
公开(公告)号：US09196315B2
公开(公告)日：2015-11-24
申请号：US13681133
申请日：2012-11-19
申请人： Teng-Hao Yeh , Yen-Hao Shih , Yan-Ru Chen
发明人： Teng-Hao Yeh , Yen-Hao Shih , Yan-Ru Chen
IPC分类号： G11C11/34 , G11C5/06 , H01L21/28 , H01L29/792 , H01L27/115 , G11C16/04
CPC分类号： G11C5/06 , G11C5/063 , G11C16/0483 , G11C2213/71 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.
摘要翻译：集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。水平延伸部分可以在凹槽中。水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

93. 发明授权

US09035369B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US09035369B2
公开(公告)日：2015-05-19
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

94. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

95. 发明授权

US08674410B2 Method of manufacturing metal silicide and semiconductor structure using the same 有权
标题翻译：使用其制造金属硅化物和半导体结构的方法
公开(公告)号：US08674410B2
公开(公告)日：2014-03-18
申请号：US13413951
申请日：2012-03-07
申请人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
发明人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
IPC分类号： H01L27/118 , H01L29/78 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/283 , H01L21/28052 , H01L21/28123 , H01L21/823443 , H01L27/1052 , H01L29/4933
摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
摘要翻译：以下公开了金属硅化物的制造方法。证明具有第一区域和第二区域的衬底。在衬底上形成硅层。进行平面化处理以使硅层具有平坦表面。去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。金属硅化物形成在第一栅极和第二栅极的顶表面上。

96. 发明申请

US20140042629A1 SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US20140042629A1
公开(公告)日：2014-02-13
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

97. 发明申请

US20140021628A1 METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE 有权
标题翻译：在三维堆叠IC器件中形成中间层连接器的方法
公开(公告)号：US20140021628A1
公开(公告)日：2014-01-23
申请号：US13607555
申请日：2012-09-07
申请人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
发明人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L23/53271 , H01L23/5329 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
摘要翻译：一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接器。通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。。。用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。中间层连接器形成在接触开口中。

98. 发明授权

US08633099B1 Method for forming interlayer connectors in a three-dimensional stacked IC device 有权
标题翻译：在三维叠层IC器件中形成层间连接器的方法
公开(公告)号：US08633099B1
公开(公告)日：2014-01-21
申请号：US13607555
申请日：2012-09-07
申请人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
发明人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
IPC分类号： H01L21/44 , H01L21/4763 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L23/53271 , H01L23/5329 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
摘要翻译：一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接。通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。。。用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。中间层连接器形成在接触开口中。

99. 发明授权

US08574992B2 Contact architecture for 3D memory array 有权
标题翻译： 3D内存阵列的联系架构
公开(公告)号：US08574992B2
公开(公告)日：2013-11-05
申请号：US13240568
申请日：2011-09-22
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , G11C5/06
CPC分类号： H01L27/11206 , H01L27/0688 , H01L27/10 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L27/2481
摘要： A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
摘要翻译：描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。可以使用相同的材料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

100. 发明申请

US20130234210A1 METHOD OF MANUFACTURING METAL SILICIDE AND SEMICONDUCTOR STRUCTURE USING THE SAME 有权
标题翻译：使用其制造金属硅化物和半导体结构的方法
公开(公告)号：US20130234210A1
公开(公告)日：2013-09-12
申请号：US13413951
申请日：2012-03-07
申请人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
发明人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
IPC分类号： H01L27/118 , H01L21/82
CPC分类号： H01L21/283 , H01L21/28052 , H01L21/28123 , H01L21/823443 , H01L27/1052 , H01L29/4933
摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
摘要翻译：以下公开了金属硅化物的制造方法。证明具有第一区域和第二区域的衬底。在衬底上形成硅层。进行平面化处理以使硅层具有平坦表面。去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。金属硅化物形成在第一栅极和第二栅极的顶表面上。

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