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91. 发明授权

US08674410B2 Method of manufacturing metal silicide and semiconductor structure using the same 有权
标题翻译：使用其制造金属硅化物和半导体结构的方法
公开(公告)号：US08674410B2
公开(公告)日：2014-03-18
申请号：US13413951
申请日：2012-03-07
申请人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
发明人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
IPC分类号： H01L27/118 , H01L29/78 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/283 , H01L21/28052 , H01L21/28123 , H01L21/823443 , H01L27/1052 , H01L29/4933
摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
摘要翻译：以下公开了金属硅化物的制造方法。证明具有第一区域和第二区域的衬底。在衬底上形成硅层。进行平面化处理以使硅层具有平坦表面。去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。金属硅化物形成在第一栅极和第二栅极的顶表面上。

92. 发明申请

US20140042629A1 SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US20140042629A1
公开(公告)日：2014-02-13
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

93. 发明申请

US20140021628A1 METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE 有权
标题翻译：在三维堆叠IC器件中形成中间层连接器的方法
公开(公告)号：US20140021628A1
公开(公告)日：2014-01-23
申请号：US13607555
申请日：2012-09-07
申请人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
发明人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L23/53271 , H01L23/5329 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
摘要翻译：一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接器。通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。。。用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。中间层连接器形成在接触开口中。

94. 发明授权

US08633099B1 Method for forming interlayer connectors in a three-dimensional stacked IC device 有权
标题翻译：在三维叠层IC器件中形成层间连接器的方法
公开(公告)号：US08633099B1
公开(公告)日：2014-01-21
申请号：US13607555
申请日：2012-09-07
申请人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
发明人： Yen-Hao Shih , Shih-Hung Chen , Teng-Hao Yeh , Chih-Wei Hu , Feng-Nien Tsai , Lo-Yueh Lin
IPC分类号： H01L21/44 , H01L21/4763 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L23/53271 , H01L23/5329 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
摘要翻译：一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接。通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。。。用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。中间层连接器形成在接触开口中。

95. 发明授权

US08574992B2 Contact architecture for 3D memory array 有权
标题翻译： 3D内存阵列的联系架构
公开(公告)号：US08574992B2
公开(公告)日：2013-11-05
申请号：US13240568
申请日：2011-09-22
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , G11C5/06
CPC分类号： H01L27/11206 , H01L27/0688 , H01L27/10 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L27/2481
摘要： A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
摘要翻译：描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。可以使用相同的材料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

96. 发明申请

US20130234210A1 METHOD OF MANUFACTURING METAL SILICIDE AND SEMICONDUCTOR STRUCTURE USING THE SAME 有权
标题翻译：使用其制造金属硅化物和半导体结构的方法
公开(公告)号：US20130234210A1
公开(公告)日：2013-09-12
申请号：US13413951
申请日：2012-03-07
申请人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
发明人： Yen-Hao Shih , Ying-Tso Chen , Shih-Chang Tsai , Chun-Fu Chen
IPC分类号： H01L27/118 , H01L21/82
CPC分类号： H01L21/283 , H01L21/28052 , H01L21/28123 , H01L21/823443 , H01L27/1052 , H01L29/4933
摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
摘要翻译：以下公开了金属硅化物的制造方法。证明具有第一区域和第二区域的衬底。在衬底上形成硅层。进行平面化处理以使硅层具有平坦表面。去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。金属硅化物形成在第一栅极和第二栅极的顶表面上。

97. 发明申请

US20130075802A1 CONTACT ARCHITECTURE FOR 3D MEMORY ARRAY 有权
标题翻译： 3D存储阵列的联系架构
公开(公告)号：US20130075802A1
公开(公告)日：2013-03-28
申请号：US13240568
申请日：2011-09-22
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L27/085 , H01L21/28
CPC分类号： H01L27/11206 , H01L27/0688 , H01L27/10 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L27/2481
摘要： A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
摘要翻译：描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。可以使用相同的材料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

98. 发明授权

US07754553B2 Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same 有权
标题翻译：具有两个分离的非导电电荷捕获插入物的电荷俘获存储器件及其制造方法
公开(公告)号：US07754553B2
公开(公告)日：2010-07-13
申请号：US12004943
申请日：2007-12-20
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.
摘要翻译：公开了具有两个分开的非导电电荷捕获插入物的电荷捕获存储器件。电荷捕获存储器件具有带有两个结的硅衬底。在硅衬底的顶部和两个结之间形成栅极氧化物（GOX）。在GOX上定义了多晶硅栅极。在硅衬底的顶部上生长一层底部氧化物（BOX），沿多晶硅栅极的底部和侧壁生长顶部氧化物（TOX）的共形层。两个充电陷阱插件位于GOX旁边和BOX和TOX之间。多晶硅栅极需要至少部分地在两个电荷捕获插入物中的每一个上。电荷捕获插入物由非导电电荷捕获材料制成。还描述了制造这种装置的方法。

99. 发明授权

US07754545B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07754545B2
公开(公告)日：2010-07-13
申请号：US11949090
申请日：2007-12-03
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L21/339 , H01L21/84
CPC分类号： H01L27/11573 , H01L21/3144
摘要： A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.
摘要翻译：提供半导体器件及其制造方法。首先，在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。接下来，氮化物层被氧化。氮化物层中的氮化物的一部分移动到第一氧化物层和基底。氮化物层的上部被转换为上部氧化物层。然后，除去第二区域中的上氧化物层，氮化物层和第一氧化物层。其次，在第二区域的基底上生长第二氧化物层。第二区域中的氮化物移动到第二氧化物层。

100. 发明授权

US07638393B2 Non-volatile memory device including nitrogen pocket implants and methods for making the same 有权
标题翻译：包括氮气袋植入物的非易失性记忆装置及其制造方法
公开(公告)号：US07638393B2
公开(公告)日：2009-12-29
申请号：US11381307
申请日：2006-05-02
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.
摘要翻译：在非易失性存储器结构中，源极/漏极区域被氮掺杂区域包围。结果，在氮掺杂区上方的衬底和电荷俘获层之间的界面被多个氮原子钝化。氮原子可以提高循环非易失性存储器件的数据保留性能和性能。

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