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91. 发明申请

US20110012083A1 PHASE CHANGE MEMORY CELL STRUCTURE 有权
标题翻译：相变存储器单元结构
公开(公告)号：US20110012083A1
公开(公告)日：2011-01-20
申请号：US12534599
申请日：2009-08-03
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

92. 发明授权

US07639527B2 Phase change memory dynamic resistance test and manufacturing methods 有权
标题翻译：相变记忆动态电阻测试及制造方法
公开(公告)号：US07639527B2
公开(公告)日：2009-12-29
申请号：US11970348
申请日：2008-01-07
申请人： Ming-Hsiu Lee , Bipin Rajendran , Chung Hon Lam
发明人： Ming-Hsiu Lee , Bipin Rajendran , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50008 , Y10T29/49004
摘要： A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.
摘要翻译：用于测试集成电路存储器件的方法包括将测试脉冲序列应用于器件上的存储器单元，其中测试脉冲导致具有取决于测试脉冲的幅度的存储器单元的电流。响应于测试脉冲的顺序测量存储器单元中的电阻。从电阻测量中提取参数集，其包括至少一个数值系数，其模拟所测量的电阻对通过存储器单元的电流的振幅的依赖性。提取的数值系数或系数与存储器件相关联，并用于控制制造操作。

93. 发明申请

US20090231942A1 THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US20090231942A1
公开(公告)日：2009-09-17
申请号：US12471411
申请日：2009-05-25
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： G11C8/00 , G11C5/06
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
摘要翻译：公开了访问存储器单元的方法。第一信号被发送到至少一个层选择晶体管。基于第一信号激活至少一个层选择晶体管。基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

94. 发明申请

US20080165573A1 Memory including two access devices per phase change element 有权
标题翻译：每个相变元件包含两个存取设备的存储器
公开(公告)号：US20080165573A1
公开(公告)日：2008-07-10
申请号：US11651157
申请日：2007-01-09
申请人： Thomas Nirschl , Roger Cheek , Mark Lamorey , Ming-Hsiu Lee
发明人： Thomas Nirschl , Roger Cheek , Mark Lamorey , Ming-Hsiu Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/74 , G11C2213/79
摘要： A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.
摘要翻译：存储器包括位线和相变元件。相变元件的第一侧耦合到位线。存储器包括耦合到相变元件的第二侧的第一存取装置和耦合到相变元件的第二侧的第二存取装置。存储器包括用于对位线进行预充电的电路和仅选择第一存取装置以将相变元件编程为第一状态的电路，并且选择第一存取装置和第二存取装置以将相变元件编程为第二州。

95. 发明授权

US07161831B2 Leaf plot analysis technique for multiple-side operated devices 有权
标题翻译：多面操作装置的叶片分析技术
公开(公告)号：US07161831B2
公开(公告)日：2007-01-09
申请号：US11150799
申请日：2005-06-10
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475
摘要： A method for analyzing the interaction between threshold states of a multiple-bit memory cell on a coordinate system is provided. The coordinate system is formed using a plurality of axes with one axis being a threshold state of a first side of a memory cell and the second axis being a threshold state of a second side of a multiple-bit memory cell. An operation is initiated on the first side of the memory cell from a start point and continues to a first target point of the first side. Then, a trace is plotted from the start point of the first side of the memory cell to a target point of the first side of the memory cell. This plot illustrates the interaction of the threshold state of the first side of the memory cell to the threshold state of the second side of the memory cell.
摘要翻译：提供了一种用于分析坐标系上的多位存储器单元的阈值状态之间的相互作用的方法。坐标系由多个轴构成，一个轴是存储单元的第一侧的阈值状态，第二轴是多位存储单元的第二侧的阈值状态。从存储器单元的起始点开始操作，并且继续到第一侧的第一目标点。然后，从存储器单元的第一侧的起始点到存储器单元的第一侧的目标点绘制迹线。该图示出了存储器单元的第一侧的阈值状态与存储器单元的第二侧的阈值状态的相互作用。

96. 发明授权

US07088613B2 Method for controlling current during read and program operations of programmable diode 有权
标题翻译：用于在可编程二极管的读取和编程操作期间控制电流的方法
公开(公告)号：US07088613B2
公开(公告)日：2006-08-08
申请号：US10846006
申请日：2004-05-14
申请人： Hang-Ting Lue , Ming-Hsiu Lee
发明人： Hang-Ting Lue , Ming-Hsiu Lee
IPC分类号： G11C11/36
CPC分类号： G11C5/147
摘要： A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.
摘要翻译：提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。该方法包括将第一电压施加到字线解码晶体管的第一栅极。该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。该方法还包括将位线解码晶体管的源电压保持在大约零。

97. 发明授权

US08779408B2 Phase change memory cell structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US08779408B2
公开(公告)日：2014-07-15
申请号：US13436203
申请日：2012-03-30
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

98. 发明申请

US20140036570A1 OPERATING METHOD FOR MEMORY DEVICE AND MEMORY ARRAY AND OPERATING METHOD FOR THE SAME 有权
标题翻译：用于存储器件和存储器阵列的操作方法及其操作方法
公开(公告)号：US20140036570A1
公开(公告)日：2014-02-06
申请号：US13567750
申请日：2012-08-06
申请人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
发明人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/004 , G11C2013/0047 , G11C2013/0052 , G11C2013/0073 , G11C2213/77
摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.
摘要翻译：提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。存储器件的操作方法包括以下步骤。使存储器件处于置位状态。用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。读取设置状态的存储器件。一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。将恢复的偏置电压施加到存储器件。在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

99. 发明申请

US20130242648A1 APPROACH FOR PHASE CHANGE MEMORY CELLS TARGETING DIFFERENT DEVICE SPECIFICATIONS 有权
标题翻译：相位改变记忆细胞的方法，针对不同的设备规格
公开(公告)号：US20130242648A1
公开(公告)日：2013-09-19
申请号：US13421718
申请日：2012-03-15
申请人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
发明人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C13/0004 , G11C13/0033 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.
摘要翻译：存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。该方法包括改变相变材料的第一有界区域的开关体积的化学成分。该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。第一保留性与第二保留性不同。

100. 发明申请

US20120187362A1 Phase Change Memory Cell Structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US20120187362A1
公开(公告)日：2012-07-26
申请号：US13436203
申请日：2012-03-30
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

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