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91. 发明申请

US20060206679A1 System and method for read synchronization of memory modules 有权
公开(公告)号：US20060206679A1
公开(公告)日：2006-09-14
申请号：US11432060
申请日：2006-05-10
申请人： Joseph Jeddeloh , Paul LaBerge
发明人： Joseph Jeddeloh , Paul LaBerge
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F1/12 , G06F13/1689
摘要： A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

92. 发明申请

US20060195647A1 System and method for memory hub-based expansion bus 有权
公开(公告)号：US20060195647A1
公开(公告)日：2006-08-31
申请号：US11399905
申请日：2006-04-07
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/00
CPC分类号： G06F13/4022 , G06F13/4234 , G06F13/4247 , Y10S370/912
摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

93. 发明申请

US20060190671A1 Memory device and method having multiple internal data buses and memory bank interleaving 有权
标题翻译：具有多个内部数据总线和存储器组交错的存储器件和方法
公开(公告)号：US20060190671A1
公开(公告)日：2006-08-24
申请号：US11064543
申请日：2005-02-23
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of internal read data buses. A first set of multiplexers selectively couple each of the internal write data buses to any of a plurality of banks of memory cells. Similarly, a second set of multiplexers selectively couple each of the banks of memory cells to any of the internal read data buses. Write data can be coupled to one of the banks concurrently with coupling read data from another of the banks. Also, write data may be concurrently coupled from respective write data buses to two different banks, and read data may be concurrently coupled from two different banks to respective read data buses.
摘要翻译：存储器件和方法通过单向下游总线接收写入数据，并通过单向上行总线输出读取数据。下游总线耦合到一对内部写入数据总线，并且上游总线耦合到一对内部读取数据总线。第一组多路复用器选择性地将每个内部写入数据总线耦合到多个存储单元组中的任一个。类似地，第二组多路复用器选择性地将每个存储器单元组耦合到任何内部读取数据总线。写入数据可以通过耦合来自另一个存储体的读取数据来同时耦合到一个存储体。而且，写入数据可以从相应的写入数据总线同时耦合到两个不同的存储体，并且读取数据可以从两个不同的存储体同时耦合到相应的读取数据总线。

94. 发明申请

US20060174070A1 Memory hub bypass circuit and method 有权
标题翻译：内存集线器旁路电路及方法
公开(公告)号：US20060174070A1
公开(公告)日：2006-08-03
申请号：US11398018
申请日：2006-04-04
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/14
CPC分类号： G06F13/1642 , G06F13/161 , G06F13/1684
摘要： A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.
摘要翻译：一种用于使用存储器集线器从多个存储器件访问数据的计算机系统和方法。计算机系统包括耦合到存储器集线器控制器的多个存储器模块。每个存储器模块包括存储器集线器和多个存储器件。存储器集线器包括定序器和旁路电路。当存储器集线器正忙于服务一个或多个存储器请求时，定序器生成并将存储器请求耦合到存储器件。当存储器集线器不忙于服务多个存储器请求时，旁路电路产生并将每个存储器请求的一部分耦合到存储器件，并且定序器产生并将每个存储器请求的剩余部分耦合到存储器件。

95. 发明授权

US07017022B2 Processing memory requests in a pipelined memory controller 失效
标题翻译：处理流水线内存控制器中的内存请求
公开(公告)号：US07017022B2
公开(公告)日：2006-03-21
申请号：US10830872
申请日：2004-04-23
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/00
CPC分类号： F02M27/06 , F02M31/14 , G06F9/3824 , Y02T10/126
摘要： A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.
摘要翻译：一种在流水线中处理多个存储器请求的方法。每个存储器请求被部分地由多个级处理。在第一阶段，存储器请求被解码。在第二阶段，处理存储器请求的地址信息。在第三阶段，传送存储器请求的数据。在每个存储器请求的处理期间，使用请求缓冲器来保存每个存储器请求。

96. 发明申请

US20060036828A1 Memory device sequencer and method supporting multiple memory device clock speeds 有权
公开(公告)号：US20060036828A1
公开(公告)日：2006-02-16
申请号：US11211848
申请日：2005-08-24
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F13/00
CPC分类号： G06F13/1689
摘要： A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the signals will be coupled to a memory device. The sequencer load unit loads the signals into the matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system. A first in, first out (“FIFO”) buffer receives the memory device signals from the sequence state matrix at a rate corresponding to the frequency of the system clock signal. A command selector transfers the memory device signals from the FIFO buffer to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.

97. 发明申请

US20050216648A1 System and method for memory hub-based expansion bus 有权
标题翻译：基于内存集线器的扩展总线的系统和方法
公开(公告)号：US20050216648A1
公开(公告)日：2005-09-29
申请号：US10810229
申请日：2004-03-25
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/4234 , G06F13/4247 , Y10S370/912
摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
摘要翻译：系统存储器包括存储器集线器控制器，存储器集线器控制器可访问的存储器模块以及具有耦合到存储器模块并且还具有对存储器模块的访问的处理器电路的扩展模块。存储器集线器控制器通过存储器总线的第一部分耦合到存储器集线器，存储器总线的存储器请求来自存储器集线器控制器，并且来自存储器集线器的存储器响应被耦合。存储器总线的第二部分将存储器集线器耦合到处理器电路，并且用于将来自处理器电路的存储器请求和由存储器集线器提供的存储器响应耦合到处理器电路。

98. 发明授权

US06934813B1 System and method for caching data based on identity of requestor 有权
标题翻译：基于请求者身份缓存数据的系统和方法
公开(公告)号：US06934813B1
公开(公告)日：2005-08-23
申请号：US10651021
申请日：2003-08-27
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888
摘要： In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.
摘要翻译：在具有制造存储器请求的多个资源的计算机或微处理器系统中，缓存系统包括源标签生成器，其根据实施例可以驻留在请求系统资源中，总线仲裁器中，或者总线仲裁器仲裁者和仲裁者或其他地方。该系统还包括能够使用源标签来实现可缓存性决定的高速缓存控制电路。高速缓存控制电路以及因此的高速缓存性能决定可以是固定的，例如由用户固定，或者可以基于合适的算法进行修改 - 类似于例如监视缓存使用和存储器的最近最近使用的算法要求。缓存系统在被控制的高速缓存足够高以缓存I / O和类似请求的结果以及请求资源是计算机系统的核心逻辑芯片组之外的I / O或类似资源时特别有用。

99. 发明申请

US20050177677A1 Arbitration system having a packet memory and method for memory responses in a hub-based memory system 有权
标题翻译：具有分组存储器的仲裁系统和用于基于集线器的存储器系统中的存储器响应的方法
公开(公告)号：US20050177677A1
公开(公告)日：2005-08-11
申请号：US10773520
申请日：2004-02-05
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1642
摘要： A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output.
摘要翻译：存储器集线器模块包括接收存储器请求的解码器，确定与每个存储器请求相关联的存储器请求标识符。分组存储器接收存储器请求标识符并存储存储器请求标识符。分组跟踪器接收远程存储器响应，并将每个远程存储器响应与存储器请求标识符相关联，并从分组存储器中移除存储器请求标识符。多路复用器接收远程存储器响应和本地存储器响应。多路复用器响应于控制信号选择输出。仲裁控制逻辑耦合到多路复用器和分组存储器，并开发控制信号以选择用于输出的存储器响应。

100. 发明申请

US20050066137A1 Method and system for controlling memory accesses to memory modules having a memory hub architecture 有权
标题翻译：用于控制对具有存储器集线器架构的存储器模块的存储器访问的方法和系统
公开(公告)号：US20050066137A1
公开(公告)日：2005-03-24
申请号：US10963824
申请日：2004-10-12
申请人： Joseph Jeddeloh , Terry Lee
发明人： Joseph Jeddeloh , Terry Lee
IPC分类号： G06F13/16 , G06F20060101 , G06F12/00 , G06F12/02 , G06F12/06 , G11C5/00
CPC分类号： G06F13/1642 , G06F13/1673
摘要： A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
摘要翻译：计算机系统包括耦合到多个存储器模块的存储器集线器控制器。存储器集线器控制器包括将存储器请求和对应的请求标识符耦合到存储器模块的存储器请求队列。每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

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