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91. 发明授权

US06629786B1 Active control of developer time and temperature 失效
标题翻译：主动控制显影时间和温度
公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节开发过程的时间和温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的显影进展。该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。处理器选择性地控制加热装置，以调节晶片各部分的温度。

92. 发明授权

US06612319B1 Low defect EBR nozzle 有权
标题翻译：低缺陷EBR喷嘴
公开(公告)号：US06612319B1
公开(公告)日：2003-09-02
申请号：US09634670
申请日：2000-08-08
申请人： Bharath Rangarajan , Khoi A. Phan , Ursula Q. Quinto
发明人： Bharath Rangarajan , Khoi A. Phan , Ursula Q. Quinto
IPC分类号： B08B302
CPC分类号： H01L21/6708 , B05B15/52 , B05B15/531 , B05B15/55 , Y10S134/902
摘要： An edge bead removal system and method is provided that employs a nozzle for applying edge bead removal solvent to an edge bead of a photoresist material layer disposed on a wafer. The nozzle includes a liquid chamber that can be connected to a supply of edge bead removal and an air supply chamber that can be connected to a supply of air. The supply of air is isolated from the liquid supply chamber during application of the edge bead removal solvent and communicates via the air supply chamber to the liquid supply chamber after application of the edge bead removal solvent thus removing any droplets of edge bead removal solvent remaining in the nozzle tip. A system is also provided that includes an absorbent material that moves from a rest position, during application of the edge bead removal solvent, to an absorbing position that removes or catches any droplets of edge bead removal solvent remaining on the nozzle tip after application of the edge bead removal solvent is completed. A nozzle is also provided that includes a liquid supply chamber with an inner cylindrical surface that is made of or coated with either a hydrophobic material and/or a hydrophilic material.
摘要翻译：提供了一种边缘珠去除系统和方法，其采用用于将边缘珠去除溶剂施加到设置在晶片上的光致抗蚀剂材料层的边缘珠的喷嘴。喷嘴包括可以连接到边缘珠移除的供应的液体室和可以连接到空气供应的空气供应室。在施加边缘珠去除溶剂期间，空气的供应与液体供应室隔离，并且在施加边缘珠粒去除溶剂之后通过供气室与液体供应室连通，从而除去剩余的边缘珠去除溶剂中的任何液滴喷嘴尖端。还提供了一种系统，其包括吸收材料，其在施加边缘珠去除溶剂期间从静止位置移动到吸收位置，该吸收位置在施加之后移除或捕获留在喷嘴尖端上的边缘珠去除溶剂的任何液滴边缘珠去除溶剂完成。还提供了一种喷嘴，其包括具有由疏水材料和/或亲水材料制成或涂覆有内部圆柱形表面的液体供应室。

93. 发明授权

US06594024B1 Monitor CMP process using scatterometry 有权
标题翻译：使用散点法监测CMP过程
公开(公告)号：US06594024B1
公开(公告)日：2003-07-15
申请号：US09886863
申请日：2001-06-21
申请人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Carmen Morales
发明人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Carmen Morales
IPC分类号： G01B1128
CPC分类号： B24B37/005 , B24B49/12 , G01N21/47 , G01N21/9501 , H01L21/30625
摘要： One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.
摘要翻译：本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统，以便确定包括晶片的CMP工艺端点，其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库，以确定晶片的状态。另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法，其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。

94. 发明授权

US06556303B1 Scattered signal collection using strobed technique 有权
标题翻译：使用频闪技术分散信号采集
公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

95. 发明授权

US06552790B1 System and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay 有权
标题翻译：用于通过减轻掩模旋转对覆盖层的影响来促进晶片对准的系统和方法
公开(公告)号：US06552790B1
公开(公告)日：2003-04-22
申请号：US09788905
申请日：2001-02-20
申请人： Michael K. Templeton , Bharath Rangarajan
发明人： Michael K. Templeton , Bharath Rangarajan
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G03F9/7003 , G03F9/7076 , G03F9/7084
摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design, and a first and second set of scribe marks. The first and second sets of scribe marks have an associated symmetry relative to the reticle design. The design and scribe marks are printed at selected field locations on a surface layer of the wafer. The first and second sets of scribe marks as printed at adjacent fields on the surface layer of wafer form a composite set of scribe marks. The symmetric relationship between the first and second sets of scribe marks results in the composite set of scribe marks substantially negating print errors of the marks due to reticle rotation and/or lens magnification with respect to a geometric reference point of the composite set of scribe marks. The employment of the composite set of scribe marks, such as to locate a corresponding virtual alignment mark, substantially facilitates mitigation of overlay error in wafer alignment.
摘要翻译：本发明涉及晶圆对准。使用掩模版，其包括设计，以及第一和第二组划线标记。第一组和第二组划痕具有相对于标线设计的相关对称性。设计和划痕被印在晶片的表面层上的选定的场地。在晶片表面层上的相邻场印刷的第一组和第二组刻痕形成一组复合的划线标记。第一组和第二组划线标记之间的对称关系导致划线标记的复合组合基本上抵消了由于标线转动和/或透镜倍率而导致的标记的印刷误差相对于复合组划线标记的几何参考点。使用复合组划线标记，例如定位相应的虚拟对准标记，基本上有助于减轻晶片对准中的重叠误差。

96. 发明授权

US06537866B1 Method of forming narrow insulating spacers for use in reducing minimum component size 有权
标题翻译：形成用于减小最小部件尺寸的窄绝缘间隔件的方法
公开(公告)号：US06537866B1
公开(公告)日：2003-03-25
申请号：US09691643
申请日：2000-10-18
申请人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
IPC分类号： H01L21338
CPC分类号： H01L29/66583 , H01L21/0331 , H01L21/0338 , H01L21/28123 , H01L21/31144 , H01L21/76802 , H01L21/76885
摘要： A method for forming insulating spacers for separating conducting layers in semiconductor wafer fabrication. The spacers are formed by removing portions of a protective photoresist layer through photolithography, and then through etching of exposed portions of the insulating layer. The spacers allow for fabrication of components that are smaller in size than are obtainable through conventional photolithography methods.
摘要翻译：一种在半导体晶片制造中形成用于分离导电层的绝缘间隔物的方法。通过光刻法去除保护光致抗蚀剂层的部分，然后通过蚀刻绝缘层的暴露部分来形成间隔物。间隔件允许制造尺寸小于通过常规光刻方法可获得的部件的部件。

97. 发明授权

US06528390B2 Process for fabricating a non-volatile memory device 有权
公开(公告)号：US06528390B2
公开(公告)日：2003-03-04
申请号：US09798667
申请日：2001-03-02
申请人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
发明人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

98. 发明授权

US06524944B1 Low k ILD process by removable ILD 失效
标题翻译：通过可移除ILD的低k ILD过程
公开(公告)号：US06524944B1
公开(公告)日：2003-02-25
申请号：US09617374
申请日：2000-07-17
申请人： Bharath Rangarajan , Ramkumar Subramanian , Michael K. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Michael K. Templeton
IPC分类号： H01L214763
CPC分类号： H01L21/7682
摘要： One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less. Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.
摘要翻译：本发明的一个方面涉及一种在半导体衬底上的金属线之间形成高级低k材料的方法，包括提供其上具有多条金属线的半导体衬底的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 以及加热或蚀刻半导体衬底中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括金属线之间的至少一个空气空隙的高级低k材料，先进的低k材料具有介电常数约为2或更小。本发明的另一方面涉及一种形成半导体结构的方法，包括在半导体结构上形成第一多个金属线的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 在所述旋涂材料中形成暴露金属线的一部分并沉积金属以在所述开口中形成多个金属通孔的多个开口; 在所述金属通孔的至少一部分上形成第二多个金属线; 以及加热或蚀刻半导体结构中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括至少一个空气空隙的先进的低k材料，该介电常数为约 2以下。

99. 发明授权

US06448097B1 Measure fluorescence from chemical released during trim etch 失效
标题翻译：测量在修剪蚀刻期间释放的化学物质的荧光
公开(公告)号：US06448097B1
公开(公告)日：2002-09-10
申请号：US09911236
申请日：2001-07-23
申请人： Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： H01L3126
CPC分类号： G01N21/64 , G01N2021/6417 , H01L22/26
摘要： A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.
摘要翻译：提供了一种使用荧光光谱法确定和控制半导体衬底的开发的系统和方法。本发明的一个方面涉及使用荧光光谱学来促进在光致抗蚀剂材料层的显影期间控制化学修剪蚀刻工艺的系统和方法。化学修剪蚀刻工艺包括将修剪化合物或材料施加到图案化的光致抗蚀剂上。修整组合物或材料可扩散到图案化抗蚀剂的侧面和顶部。抗蚀剂的扩散区域可溶于显影剂，这有助于在图案化的光致抗蚀剂中产生更小的特征。荧光光谱系统可用于测量孤立和致密的光栅或CD，并使用CD的演变来确定何时终止化学修饰过程。

100. 发明授权

US06444381B1 Electron beam flood exposure technique to reduce the carbon contamination 有权
标题翻译：电子束泛滥技术减少碳污染
公开(公告)号：US06444381B1
公开(公告)日：2002-09-03
申请号：US09729295
申请日：2000-12-04
申请人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
发明人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
IPC分类号： G03F900
CPC分类号： G03F1/74 , Y10S430/143
摘要： One aspect of the present invention relates to a method for reducing carbon contamination on a mask involving placing a mask plate having carbon-containing contaminants thereon in a processing chamber; simultaneously contacting the mask plate with oxygen and exposing the mask plate with a flood exposure of electron beams wherein the carbon-containing contaminants are converted to a by-product; and removing the by-product from the processing chamber.
摘要翻译：本发明的一个方面涉及一种用于减少掩模上的碳污染的方法，其涉及将具有含碳污染物的掩模板放置在处理室中; 同时使掩模板与氧气接触，并将电子束的暴露暴露于掩模板，其中含碳污染物转化为副产物; 并从处理室中除去副产物。

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