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91. 发明申请

US20070255975A1 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US20070255975A1
公开(公告)日：2007-11-01
申请号：US11819417
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。

92. 发明授权

US07281152B2 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US07281152B2
公开(公告)日：2007-10-09
申请号：US10808571
申请日：2004-03-25
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F5/06 , G06F1/00 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor includes a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, the clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量来确定时钟信号的新时钟频率，所述时钟信号被新提供给所述操作处理部分。

93. 发明申请

US20060017459A1 Programmable logic circuit apparatus and programmable logic circuit reconfiguration method 失效
标题翻译：可编程逻辑电路设备和可编程逻辑电路重构方法
公开(公告)号：US20060017459A1
公开(公告)日：2006-01-26
申请号：US11081589
申请日：2005-03-17
申请人： Shinichi Kanno , Masaya Tarui , Taku Ohneda , Riku Ogawa
发明人： Shinichi Kanno , Masaya Tarui , Taku Ohneda , Riku Ogawa
IPC分类号： H03K19/177
CPC分类号： H03K19/17752
摘要： A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.
摘要翻译：可编程逻辑电路装置包括动态地切换和操作多个电路块的可编程逻辑电路。电路块包括执行分支处理的分支电路块和对由分支电路块获得的数据选择性地执行多种处理的多个子电路块。该装置还包括存储单元，其存储由分支电路块获得的数据和输入数据的子电路块的标识符。标识符与数据相关联。该装置还包括一个控制器，该控制器使可编程逻辑电路处理与存储在存储单元中的数据相当的与可编程逻辑电路中正在操作的子电路块的标识符相同的标识符的数据，优先于数据与其他子电路块的标识符相关联。

94. 发明申请

US20050268125A1 Logic circuit apparatus 有权
标题翻译：逻辑电路装置
公开(公告)号：US20050268125A1
公开(公告)日：2005-12-01
申请号：US11128187
申请日：2005-05-13
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
IPC分类号： G06F1/32 , G06F1/08 , G06F1/30 , H03K19/00 , H03K19/173
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.
摘要翻译：可编程逻辑电路是基于电路数据的可变电路组件。电路数据存储器存储多个电路数据和性能要求。特征数据存储器存储每个可编程逻辑电路的特征数据。控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求分配给每个可编程逻辑电路的可编程逻辑电路在最小电压范围内。供电单元向多个可编程逻辑电路提供最小电压。

95. 发明申请

US20050138445A1 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US20050138445A1
公开(公告)日：2005-06-23
申请号：US10960707
申请日：2004-10-08
申请人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： H01L21/822 , G06F1/26 , G06F1/32 , H01L21/82 , H01L27/04 , H03K19/00 , H03K19/173
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.
摘要翻译：通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定时钟信号和电压，使用操作时间。

96. 发明申请

US20050110518A1 Logic circuit apparatus and timeshare operating method of a programmable logic circuit 失效
标题翻译：可编程逻辑电路的逻辑电路设备和分时运行方法
公开(公告)号：US20050110518A1
公开(公告)日：2005-05-26
申请号：US10948702
申请日：2004-09-24
申请人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
发明人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
IPC分类号： G06F11/00 , G06F9/06 , G06F15/76 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： G06F17/5054
摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.
摘要翻译：一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

97. 发明授权

US06611870B1 Server device and communication connection scheme using network interface processors 失效
标题翻译：使用网络接口处理器的服务器设备和通信连接方案
公开(公告)号：US06611870B1
公开(公告)日：2003-08-26
申请号：US09136513
申请日：1998-08-19
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F1516
CPC分类号： G06F13/385
摘要： A server device and a communication connection scheme capable of expanding the memory bandwidth and thereby expanding the power to transmit Web data to the network are disclosed. Network cards are detachably attached to a host machine (main machine). Each network card contains a processor, a memory, and a network interface unit, where data are transmitted to the network from a memory on the network card and the memory bandwidth expansion is realized by the presence of a plurality of network cards. In addition, using a memory of the network card as a cache, the load on the host machine is reduced by transmitting data from this memory to the network when the data exists on the memory and a certain condition is satisfied.
摘要翻译：公开了能够扩展存储器带宽并由此扩展将网络数据传输到网络的功能的服务器设备和通信连接方案。网卡可拆卸地连接到主机（主机）。每个网卡包含处理器，存储器和网络接口单元，其中数据从网卡上的存储器发送到网络，并且通过存在多个网卡来实现存储器带宽扩展。此外，使用网卡的存储器作为缓存，当数据存在于存储器上并且满足一定条件时，通过从该存储器向网络发送数据来减少主机上的负载。

98. 发明授权

US06295560B1 Data delivery system with load distribution among data delivery units using shared lower address and unique lower layer address 有权
标题翻译：数据传送系统在数据传送单元之间具有负载分配，使用共享的较低地址和唯一的较低层地址
公开(公告)号：US06295560B1
公开(公告)日：2001-09-25
申请号：US09205368
申请日：1998-12-04
申请人： Shinichi Kanno , Shigehiro Asano
发明人： Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F1300
CPC分类号： G06F9/5083
摘要： A data delivery system capable of distributing processing loads on the data supply side without providing the control processor, in which clients can receive data delivery without becoming conscious of the switching of processors that carry out the data delivery, is disclosed. In this data delivery system, a request from the client to the data delivery system is always received by all the data delivery units according to the shared lower layer address, while a response to the connection request is made by only one data delivery unit which has the response right at that moment using the unique lower layer address of that data delivery unit. In this way, it appears to the client as if the request is always made with respect to the same correspondent, while at the data supply side, the data delivery unit for responding to the client is appropriately switched by appropriately transferring the response right so as to realize the load distribution within the data delivery system.
摘要翻译：公开了一种能够在不提供控制处理器的情况下在数据提供侧分配处理负荷的数据传送系统，其中客户端可以在不意识到进行数据传送的处理器的切换的情况下接收数据传送。在该数据传送系统中，由所有数据传送单元总是按照共享的下层地址接收来自客户端到数据传送系统的请求，而对连接请求的响应仅由一个数据传送单元进行，此时使用该数据传送单元的唯一下层地址的响应权限。以这种方式，对于客户端来说，似乎总是针对相同的记者进行请求，而在数据提供端，通过适当地转移响应权来适当地切换用于响应客户端的数据传送单元，以便实现数据传送系统内的负载分配。

99. 发明授权

US08990480B2 Semiconductor memory device and computer program product 有权
标题翻译：半导体存储器和计算机程序产品
公开(公告)号：US08990480B2
公开(公告)日：2015-03-24
申请号：US13586219
申请日：2012-08-15
申请人： Shinichi Kanno , Kazuhiro Fukutomi
发明人： Shinichi Kanno , Kazuhiro Fukutomi
IPC分类号： G06F12/00 , G11C16/10 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block.
摘要翻译：根据实施例，半导体存储器件包括半导体存储器芯片，用于存储以页为单位写入和读取的多个数据，并且以包括多个页的块为单位被擦除; 在所述数据被写入所述半导体存储器芯片中，在所述多个数据中的至少一部分有效数据被指定的情况下，丢弃所述丢弃单元; 压缩单元，将存储在第一块中的有效数据中的排除丢弃数据的有效数据写入第二块中，并擦除第一块; 以及控制器，响应于读取丢弃的数据的请求，输出指示数据不能被读取的响应。当包含在块中的所有有效数据被丢弃时，丢弃单元擦除该块。

100. 发明授权

US08612721B2 Semiconductor memory controlling device 有权
标题翻译：半导体存储器控制装置
公开(公告)号：US08612721B2
公开(公告)日：2013-12-17
申请号：US13037970
申请日：2011-03-01
申请人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
发明人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译：根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。第一表包括指定第二表条目的信息或指定第三表条目的信息。半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。

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