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91. 发明授权

US07112837B2 MFIS ferroelectric memory array 有权
标题翻译： MFIS铁电存储器阵列
公开(公告)号：US07112837B2
公开(公告)日：2006-09-26
申请号：US11262545
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L29/76
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

92. 发明授权

US07008833B2 In2O3thin film resistivity control by doping metal oxide insulator for MFMox device applications 有权
标题翻译：用于MFMox器件应用的掺杂金属氧化物绝缘体的In2O3薄膜电阻率控制
公开(公告)号：US07008833B2
公开(公告)日：2006-03-07
申请号：US10755419
申请日：2004-01-12
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/336
CPC分类号： H01L21/28291 , H01L29/78391
摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.
摘要翻译：本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了俘获的电荷效应并导致存储保持力的提高特点电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

93. 发明授权

US06995025B2 Asymmetrical programming ferroelectric memory transistor 失效
标题翻译：非对称编程铁电存储晶体管
公开(公告)号：US06995025B2
公开(公告)日：2006-02-07
申请号：US10873326
申请日：2004-06-21
申请人： Sheng Teng Hsu , Tingkai Li
发明人： Sheng Teng Hsu , Tingkai Li
IPC分类号： H01L21/00
CPC分类号： H01L29/78391
摘要： A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the ferrorelectric memory transistor.
摘要翻译：制造和编程用于非对称编程的铁电存储晶体管的方法包括制造具有覆盖栅极区域的金属氧化物层的铁电存储晶体管; 并且对铁电存储晶体管进行编程，使得低阈值电压约等于铁电介质存储晶体管的固有阈值电压。

94. 发明授权

US06991942B1 MFIS ferroelectric memory array on SOI and method of making same 失效
标题翻译： SOI上的MFIS铁电存储阵列及其制作方法
公开(公告)号：US06991942B1
公开(公告)日：2006-01-31
申请号：US10953912
申请日：2004-09-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L21/00
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

95. 发明授权

US06887799B1 Indium oxide conductive film 失效
标题翻译：氧化铟导电膜
公开(公告)号：US06887799B1
公开(公告)日：2005-05-03
申请号：US10741803
申请日：2003-12-18
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/28291 , H01L21/31604 , H01L29/513 , H01L29/517 , H01L29/78391
摘要： One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.
摘要翻译：使用氧化铟膜（In 2 O 3 O 3），In 2 N 3 O 3的<！ - SIPO - >单晶体铁电存储器件 >膜结构，并提供相应的制造方法。用于控制In 2 N 3 O 3膜中的电阻率的方法包括：使用PVD工艺沉积In膜，通常具有200至300瓦特的功率; 形成包括在衬底材料中的膜; 同时（形成含In膜）加热衬底材料，通常将衬底加热至20至200℃的温度范围; 在形成含In膜之后，通常在O 2气氛中进行后退火; 并且响应于后退火：形成In 2 N 3 O 3膜; 并且控制In 2 N 3 O 3膜中的电阻率。例如，电阻率可以控制在260至800欧姆 - 厘米的范围内。

96. 发明授权

US06737693B2 Ferroelastic integrated circuit device 失效
标题翻译：铁磁集成电路器件
公开(公告)号：US06737693B2
公开(公告)日：2004-05-18
申请号：US10412890
申请日：2003-04-14
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

97. 发明授权

US06716645B2 MFMOS capacitors with high dielectric constant materials 有权
标题翻译：具有高介电常数材料的MFMOS电容器
公开(公告)号：US06716645B2
公开(公告)日：2004-04-06
申请号：US10319314
申请日：2002-12-12
申请人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
发明人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
IPC分类号： H01L2100
CPC分类号： H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译：用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口，设备的可靠性。

98. 发明授权

US06703655B2 Ferroelectric memory transistor 失效
标题翻译：铁电存储晶体管
公开(公告)号：US06703655B2
公开(公告)日：2004-03-09
申请号：US10385038
申请日：2003-03-10
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2976
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/11502 , H01L29/78391
摘要： A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack. A method of forming a ferroelectric memory transistor includes preparing a substrate, including forming active regions and an oxide device isolation region; forming a gate placeholder structure in a gate region; removing the gate placeholder structure forming a gate void in the gate region; depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup; filling the high-k cup with a ferroelectric material to form a ferroelectric element; depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element; depositing a top electrode over the high-k cap to form a gate electrode and gate stack; depositing a layer of passivation oxide over the structure; etching the passivation oxide to from contact vias to the active regions and the gate stack; and metallizing the structure to complete the ferroelectric memory transistor.
摘要翻译：铁电存储晶体管包括其中具有有源区的衬底; 包括：高k绝缘体元件，包括高k杯和高k帽; 铁电元件，其中所述铁电元件封装在所述高k绝缘体元件内; 以及位于所述高k绝缘体的顶部上的顶电极; 位于衬底和栅极叠层上方的钝化氧化物层; 以及金属化以形成与有源区和栅叠层的接触。形成铁电存储晶体管的方法包括：制备基片，包括形成有源区和氧化物器件隔离区; 在栅极区域形成栅极占位符结构; 去除在栅极区域中形成栅极空隙的栅极占位符结构; 在结构上和栅极空隙中沉积高k绝缘体层以从高k杯沉积; 用铁电材料填充高k杯以形成铁电元件; 沉积高k上绝缘体层并去除多余的高k材料以在铁电元件上形成高k帽; 在顶部电极上沉积高k帽以形成栅电极和栅叠层; 在结构上沉积一层钝化氧化物; 将钝化氧化物从接触孔蚀刻到有源区和栅叠层; 并且对结构进行金属化以完成铁电存储晶体管。

99. 发明授权

US06649957B2 Thin film polycrystalline memory structure 失效
标题翻译：薄膜多晶记忆结构
公开(公告)号：US06649957B2
公开(公告)日：2003-11-18
申请号：US10345725
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
IPC分类号： H01L2976
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
摘要翻译：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了形成多晶存储器结构的方法。沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

100. 发明授权

US06534326B1 Method of minimizing leakage current and improving breakdown voltage of polycrystalline memory thin films 失效
标题翻译：最小化漏电流并提高多晶记忆薄膜的击穿电压的方法
公开(公告)号：US06534326B1
公开(公告)日：2003-03-18
申请号：US10099186
申请日：2002-03-13
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
IPC分类号： H01L2100
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
摘要翻译：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了形成多晶存储器结构的方法。沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

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