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91. 发明申请

US20120319191A1 PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE 审中-公开
标题翻译：制造包含充电平衡柱结构和相关器件的半导体电源装置的方法
公开(公告)号：US20120319191A1
公开(公告)日：2012-12-20
申请号：US13597133
申请日：2012-08-28
申请人： Simona Lorenti , Cateno Marco Camalleri , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Simona Lorenti , Cateno Marco Camalleri , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L21/3247 , H01L21/02057 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/3065 , H01L21/324 , H01L27/088 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/73 , H01L29/7395 , H01L29/7802 , H01L29/8611 , H01L29/872
摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.
摘要翻译：一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

92. 发明申请

US20120187479A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20120187479A1
公开(公告)日：2012-07-26
申请号：US13434686
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

93. 发明授权

US08174076B2 Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices 有权
标题翻译：用于制造集成在半导体衬底中的电子器件和相应器件的方法
公开(公告)号：US08174076B2
公开(公告)日：2012-05-08
申请号：US12964579
申请日：2010-12-09
申请人： Ferruccio Frisina , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Mario Giuseppe Saggio
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.
摘要翻译：一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的植入源区，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理的身体和来源地区。

94. 发明申请

US20110081759A1 POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD 有权
公开(公告)号：US20110081759A1
公开(公告)日：2011-04-07
申请号：US12967845
申请日：2010-12-14
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/8232
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

95. 发明授权

US07892923B2 Power field effect transistor and manufacturing method thereof 有权
标题翻译：功率场效应晶体管及其制造方法
公开(公告)号：US07892923B2
公开(公告)日：2011-02-22
申请号：US11971111
申请日：2008-01-08
申请人： Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types suitable to complete the formation of the body region, of the source region, and of the deep implanted region with diffusing the dopants in the substrate.
摘要翻译：一种在具有宽带隙表面半导体层的宽带隙半导体衬底上制造垂直功率MOS晶体管的方法，包括以下步骤：在表面半导体层上形成屏蔽结构，该屏蔽结构使表面半导体层的多个区域暴露在所述表面半导体层中至少进行第一种类型的掺杂剂的第一离子注入，用于形成至少一个深注入区域，在所述表面半导体层中进行至少第二种类型的掺杂剂的第二离子注入以形成所述MOS晶体管的至少一个植入体区域与所述深注入区域对准，在所述表面半导体层中执行至少一种第二类型掺杂剂的离子注入，以在所述表面半导体层中至少形成所述MOS晶体管的注入源区域至少一个植入体区域，以及第一和第二植入体的低预算激活热过程适于完成体区，源区和深注入区的形成的第二掺杂剂类型，使掺杂剂扩散到衬底中。

96. 发明授权

US07790520B2 Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
标题翻译：用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构
公开(公告)号：US07790520B2
公开(公告)日：2010-09-07
申请号：US12641189
申请日：2009-12-17
申请人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
发明人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
IPC分类号： H01L21/332
CPC分类号： H01L29/7811 , H01L21/324 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/0692 , H01L29/0847 , H01L29/41766 , H01L29/66128 , H01L29/66727 , H01L29/66734 , H01L29/73 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.
摘要翻译：制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。边缘终端结构通过以下方式形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电连接到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

97. 发明授权

US07569883B2 Switching-controlled power MOS electronic device 有权
标题翻译：开关控制功率MOS电子器件
公开(公告)号：US07569883B2
公开(公告)日：2009-08-04
申请号：US11285759
申请日：2005-11-21
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
IPC分类号： H01L29/76 , H01L29/94 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
摘要翻译：这种类型的功率电子MOS器件包括多个基本功率MOS晶体管和一个栅极结构，该栅极结构包括由第一导电材料（例如多晶硅），多个栅极指状物或连接到栅极焊盘的金属轨道至少一个与至少一个所述导电带串联布置的连接层。这种门结构包括形成在导电条的上表面上并适当地形成在连接层上的至少多个独立的岛。所述岛通过至少一种第二导电材料如硅化物实现。

98. 发明申请

US20090179263A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱结构的功率半导体器件的工艺以及相应的功率半导体器件
公开(公告)号：US20090179263A1
公开(公告)日：2009-07-16
申请号：US12298025
申请日：2006-04-21
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

99. 发明授权

US07560368B2 Insulated gate planar integrated power device with co-integrated Schottky diode and process 有权
标题翻译：具有共同集成肖特基二极管和工艺的绝缘栅平面集成功率器件
公开(公告)号：US07560368B2
公开(公告)日：2009-07-14
申请号：US11520210
申请日：2006-09-12
申请人： Angelo Magri′ , Ferruccio Frisina
发明人： Angelo Magri′ , Ferruccio Frisina
IPC分类号： H01L21/28
CPC分类号： H01L29/66719 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66712 , H01L29/66727 , H01L29/7806 , H01L29/7839 , H01L29/872
摘要： A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages. A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the co-integrated device, is also disclosed.
摘要翻译：以完全自对准的方式将构成绝缘栅功率器件的集成结构的单元的孔内的肖特基接触集成在一起的处理不需要专用的掩蔽步骤。这克服了增加集成功率器件的蜂窝结构的封装密度的可能性的限制，同时可以在器件的反极化下提高共同集成的肖特基二极管的性能并产生其他优点。还公开了一种平面集成绝缘栅功率器件，其具有构成该元件的单元的高封装密度，其具有与并联器件并联的肖特基二极管。

100. 发明授权

US06492691B2 High integration density MOS technology power device structure 有权
标题翻译：高集成度MOS技术功率器件结构
公开(公告)号：US06492691B2
公开(公告)日：2002-12-10
申请号：US09318693
申请日：1999-05-25
申请人： Angelo Magri' , Ferruccio Frisina
发明人： Angelo Magri' , Ferruccio Frisina
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/4238 , H01L29/7802
摘要： High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by junction regions, so that the at least one plurality of body stripes and the junction regions form a continuous, serpentine-shaped body region.
摘要翻译：高密度MOS技术功率器件结构，包括形成在第二导电类型的半导体层中的第一导电类型的主体区域，其中所述主体区域包括至少多个基本上直线和基本上平行的主体条，每个条带在其端部连接到相邻的身体条纹由接合区域，使得至少多个主体条纹和连接区域形成连续的蛇形形状的身体区域。

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