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91. 发明授权

US07006589B2 Frequency synthesizer with phase restart 有权
标题翻译：频率合成器，具有相位重启
公开(公告)号：US07006589B2
公开(公告)日：2006-02-28
申请号：US10008462
申请日：2001-11-30
申请人： Robert B. Staszewski , Ken Maggio
发明人： Robert B. Staszewski , Ken Maggio
IPC分类号： H04L25/00 , H04L25/40 , H04L7/00
CPC分类号： H03L7/099 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/16
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.
摘要翻译：基于频率合成器的发射机（10）包括具有各种电容器阵列的数字控制振荡器（DCO）的LC箱（12）。液相色谱箱12分为反映两种一般操作模式的两个主要组：采集和跟踪。第一组（过程/电压/温度和采集）最初初始化设置所需的中心振荡频率，而第二组（整数和分数跟踪）在实际操作期间精确地控制振荡频率。对于高精度输出，在整数跟踪控制器中使用动态元件匹配（DEM）来减少由非均匀电容值引起的非线性。此外，在获取所选择的信道之后，整数跟踪电容器阵列的优选范围可以用于调制。数字Σ-Δ调制器电路（50）响应错误字的分数位驱动电容器阵列（14d）。在模式开关上，累加误差被重新计算到相位重启值，以防止扰动。

92. 发明授权

US06734741B2 Frequency synthesizer with digitally-controlled oscillator 有权
公开(公告)号：US06734741B2
公开(公告)日：2004-05-11
申请号：US10006607
申请日：2001-11-30
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

93. 发明授权

US06636572B1 High-speed digital timing and gain gradient circuit employing a parallel architecture 有权
标题翻译：采用并行架构的高速数字定时和增益梯度电路
公开(公告)号：US06636572B1
公开(公告)日：2003-10-21
申请号：US09256420
申请日：1999-02-24
申请人： Robert B. Staszewski
发明人： Robert B. Staszewski
IPC分类号： H04L700
CPC分类号： G11B20/10 , G11B20/10009
摘要： A system and a method for implementing a feedback control signal by employing parallel paths (105 and 106) for processing separate parts of the signal. The method effectively doubles operating speed of the feedback circuit by providing two processing paths (101 and 102). Where two paths are used, each operates at approximately one-half of the data rate of the incoming data signal (516). The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (513) of a disk drive (500), three modes are desired: FIR-bypass (201), acquisition (202), and data-tracking (203). Being able to switch easily among the three modes of the system (200) provided for in a read channel of a disk drive (500) demonstrates the adaptability of the method and supporting structure to a broad class of feedback circuits used in systems employing high throughput rates.
摘要翻译：一种用于通过使用用于处理信号的分离部分的并行路径（105和106）来实现反馈控制信号的系统和方法。该方法通过提供两个处理路径（101和102）有效地使反馈电路的工作速度加倍。在使用两个路径的情况下，每个路径以输入数据信号（516）的数据速率的大约一半的速率工作。该方法还适用于那些使用多种模式的应用程序中的处理。例如，当在盘驱动器（500）的读通道（513）中使用时，需要三种模式：FIR-旁路（201），获取（202）和数据跟踪（203）。能够在盘驱动器（500）的读通道中提供的系统（200）的三种模式之间容易地切换，证明了该方法和支持结构适用于采用高吞吐量的系统中广泛使用的反馈电路价格。

94. 发明授权

US06252733B1 Method and apparatus for acquiring a preamble signal in a hard disk drive 有权
标题翻译：用于在硬盘驱动器中获取前置信号的方法和装置
公开(公告)号：US06252733B1
公开(公告)日：2001-06-26
申请号：US09247131
申请日：1999-02-09
申请人： Robert B. Staszewski
发明人： Robert B. Staszewski
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B5/012 , G11B20/10009 , G11B20/10037 , H03L7/091 , H04L7/10
摘要： The hard disk drive includes a storage media system (12) and a read channel (27) for reading data from the storage media system (12). The read channel (28) is operable to read a preamble. Also included is a phase lock loop (53) which is coupled to the read channel (28) and operable to acquire the preamble signal. The phase lock loop (53) includes a timing gradient generator (70) which is operable to determine a timing gradient using a single term timing gradient equation. Also included is a loop filter (72), coupled to the timing gradient generator (70). The loop filter (72) determines an integral timing. A voltage controlled oscillator (74) is coupled to the loop filter (72) and determines a timing phase, the timing phase representing a timing adjustment for the read channel (28).
摘要翻译：硬盘驱动器包括用于从存储介质系统（12）读取数据的存储介质系统（12）和读通道（27）。读通道（28）可操作以读取前置码。还包括锁相环（53），其耦合到读通道（28）并且可操作以获取前导码信号。锁相环（53）包括定时梯度发生器（70），其可操作以使用单项定时梯度方程来确定定时梯度。还包括耦合到定时梯度发生器（70）的环路滤波器（72）。环路滤波器（72）确定积分时序。电压控制振荡器（74）耦合到环路滤波器（72）并确定定时相位，所述定时相位表示读取通道（28）的定时调整。

95. 发明授权

US6037886A Method and apparatus for extracting band and error values from digital samples of an analog signal 失效
标题翻译：用于从模拟信号的数字样本中提取频带和误差值的方法和装置
公开(公告)号：US6037886A
公开(公告)日：2000-03-14
申请号：US53867
申请日：1998-04-01
申请人： Robert B. Staszewski , Gennady Feygin
发明人： Robert B. Staszewski , Gennady Feygin
IPC分类号： G11B20/10 , H03M1/06 , H03M1/18 , H03M1/62
CPC分类号： H03M1/0624 , G11B20/10009 , G11B20/10055 , H03M1/185
摘要： A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter. The filter not only shapes the signal spectrum, but also performs an integer space transformation that normalizes the output of the analog-to-digital converter with respect to the predetermined targets and thresholds of the band/error circuit.
摘要翻译：用于硬盘驱动系统（10）的读通道电路（27）包括具有通过滤波器（41）提供给检测器（46）的输出（39）的模拟 - 数字转换器（38），并且频带/误差电路（47）。频带/误差电路从滤波器输出提取频带值（48）和误差值（49）。频带和误差值由定时恢复环路（51,53）用于控制模数转换器的操作，并且由增益恢复回路（51,54）使用以便于自动增益控制功能用于模拟电路（36）。频带/误差电路使用各自为2的幂的目标和阈值，使得可以将来自滤波器的输出的预定数量的最低有效位用作误差值，而无需修改。从滤波器输出的最高有效位确定频带值。滤波器不仅对信号频谱进行整形，而且还执行整数空间变换，其相对于预定目标和频带/误差电路的阈值对模数转换器的输出进行归一化。

96. 发明授权

US5376847A Phase detector and methodology 失效
标题翻译：相位检测器和方法
公开(公告)号：US5376847A
公开(公告)日：1994-12-27
申请号：US998474
申请日：1992-12-30
申请人： Robert B. Staszewski
发明人： Robert B. Staszewski
IPC分类号： G01R25/00 , H03D13/00 , H03K9/06
CPC分类号： G01R25/00 , H03D13/004
摘要： In one embodiment, a method of providing phase detection from a circuit having first and second inputs and at least one output is disclosed. The method includes a cyclical operation of four steps. The first step awaits the receipt at the first input of an input signal which at least meets the requirements of one of two given binary values. The second step awaits the receipt at the first input of an input signal which at least meets the requirements of the other of the two given binary values before providing an output signal of a first value at the output. The third step awaits the receipt at the second input of an input signal which at least meets the requirements of one of two given binary values. The fourth step awaits the receipt at the second input of an input signal which at least meets the requirements of the other of the two given binary values before changing the output signal at the output to a second value. The process then returns to the first step. Apparatus in accordance with the inventive method are also described, including preferred TTL and CMOS logic diagrams for implementing a four state machine.
摘要翻译：在一个实施例中，公开了一种从具有第一和第二输入和至少一个输出的电路提供相位检测的方法。该方法包括四个步骤的循环操作。第一步等待在输入信号的第一输入处的接收，其至少满足两个给定二进制值之一的要求。在提供输出端处的第一值的输出信号之前，第二步骤等待在输入信号的第一输入处的接收，其至少满足两个给定二进制值中的另一个的要求。第三步骤等待在输入信号的第二输入处的接收，其至少满足两个给定二进制值之一的要求。在输入信号的第二输入处等待接收输入信号的第四步骤，其在将输出处的输出信号改变为第二值之前至少满足两个给定二进制值中的另一个的要求。该过程然后返回到第一步。还描述了根据本发明方法的装置，包括用于实现四状态机的优选TTL和CMOS逻辑图。

97. 发明授权

US08855236B2 Digital amplitude modulation 有权
标题翻译：数字幅度调制
公开(公告)号：US08855236B2
公开(公告)日：2014-10-07
申请号：US13237740
申请日：2011-09-20
申请人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
发明人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
IPC分类号： H03C1/52 , H04L27/36
CPC分类号： H04L27/361
摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
摘要翻译：使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

98. 发明授权

US08204107B2 Bandwidth reduction mechanism for polar modulation 有权
标题翻译：极化调制带宽减少机制
公开(公告)号：US08204107B2
公开(公告)日：2012-06-19
申请号：US12324308
申请日：2008-11-26
申请人： Jingcheng Zhuang , Robert B. Staszewski , Khurram Waheed
发明人： Jingcheng Zhuang , Robert B. Staszewski , Khurram Waheed
IPC分类号： H04B1/66
CPC分类号： H03C5/00
摘要： A novel and useful apparatus for and method of reducing phase and amplitude modulation bandwidth in polar transmitters. The bandwidth reduction mechanism of the present invention effectively reduces the phase modulation bandwidth of the polar modulation performed in the transmitter by modifying the zero-crossing trajectories in the IQ domain. This significantly reduces the phase modulation bandwidth while still meeting the output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as 3G WCDMA, etc. The mechanism detects a zero crossing or a near zero crossing within a predetermined threshold of the origin and an offset vector is generated that when added to the input TX IQ data, shifts the trajectory to avoid the origin thus reducing the resultant polar modulation amplitude and phase bandwidth.
摘要翻译：一种用于降低极化发射机相位和幅度调制带宽的新颖有用的装置和方法。本发明的带宽减小机制通过修改IQ域中的过零轨迹有效地降低了在发射机中执行的极坐标调制的相位调制带宽。这显着降低了相位调制带宽，同时仍然满足特定现代宽带无线标准（如3G WCDMA等）的输出频谱和误差矢量幅度（EVM）要求。机构检测预定的过零点或近零交叉点产生原点的阈值和偏移矢量，当添加到输入TX IQ数据时，移动轨迹以避免原点，从而减少所得到的极坐标调制幅度和相位带宽。

99. 发明授权

US08155256B2 Method and apparatus for asynchronous clock retiming 有权
标题翻译：用于异步时钟重新定时的方法和装置
公开(公告)号：US08155256B2
公开(公告)日：2012-04-10
申请号：US09969307
申请日：2001-10-02
申请人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
发明人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
IPC分类号： H04L7/00
CPC分类号： H03L7/18 , H03L7/085 , H03L7/091 , H03L2207/50
摘要： A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.
摘要翻译：使用时间到数字转换器来确定较高频率时钟（过采样时钟）的哪个边缘比较低频率定时信号的边缘更远。同时，过采样时钟通过两个寄存器执行定时信号的采样：一个在上升沿，另一个在下降沿。然后，选择由分数阶段检测器决定确定的“更好质量”重新定时的寄存器，以提供重定时输出。

100. 发明授权

US07817747B2 Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter 有权
标题翻译：数字极化发射机中幅度和相位/频率调制路径之间的精确延迟对准
公开(公告)号：US07817747B2
公开(公告)日：2010-10-19
申请号：US11675565
申请日：2007-02-15
申请人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
发明人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
IPC分类号： H04L27/36
CPC分类号： H04L27/368 , H03C5/00 , H04L7/0029 , H04L7/0041 , H04L7/005 , H04L7/0079 , H04L7/02
摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.
摘要翻译：数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。本发明提供了一种全数字延迟对准机构，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。

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