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91. 发明授权

US07557651B2 Dual transconductance amplifiers and differential amplifiers implemented using such dual transconductance amplifiers 有权
标题翻译：使用这种双跨导放大器实现的双跨导放大器和差分放大器
公开(公告)号：US07557651B2
公开(公告)日：2009-07-07
申请号：US11670564
申请日：2007-02-02
申请人： Marco Corsi
发明人： Marco Corsi
IPC分类号： H03F3/45
CPC分类号： H03F3/45094 , H03F3/45475 , H03F3/45968 , H03F2203/45082 , H03F2203/45138 , H03F2203/45212 , H03F2203/45288 , H03F2203/45418 , H03F2203/45722
摘要： Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.
摘要翻译：公开了用于信号放大的各种系统和方法。例如，本发明的一些实施例提供了包括双跨导特性的差分放大器。这种放大器包括两个双输入运算放大器，每个放大器包括两个输入组。输入组中的第一个展现出第一跨导，并且输入组中的第二个展现出第二跨导。两个双输入运算放大器被配置为使得对于共模信号，放大器表现出作为第一跨导和第二跨导之间的差异的总跨导。相比之下，对于差分信号，总跨导是第一跨导与第二跨导之和。

92. 发明申请

US20090039923A1 TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION 有权
标题翻译：具有低失真的跟踪和保持电路
公开(公告)号：US20090039923A1
公开(公告)日：2009-02-12
申请号：US11876943
申请日：2007-10-23
申请人： Marco Corsi , Robert Payne
发明人： Marco Corsi , Robert Payne
IPC分类号： G11C27/02
CPC分类号： G11C27/026 , H03M1/0624 , H03M1/1245
摘要： A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant. A second capacitor is provided, having a first terminal connected to the first terminal of the resistor and having a second terminal connected to a power supply terminal. The second capacitor substantially reduces frequency-dependent harmonic distortion.
摘要翻译：跟踪和保持电路，其能够跟踪模拟输入信号，并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。提供了第一电容器，其具有连接到电源端子的第一端子。当处于导通状态时，跟踪电路通过将跟踪电压施加到电阻器的第一端，通过电阻器向第一电容器的与模拟输入信号的电压相对应的第二端施加跟踪电压，第二电阻器的端子连接到第一电容器的第二端子。响应于轨道信号和保持信号的开关操作以响应于轨道信号将跟踪电路切换到接通状态，并且响应于保持信号而将其切换到关闭状态，从轨道信号变为时间保持信号包括采样时刻。提供了第二电容器，其具有连接到电阻器的第一端子的第一端子，并且具有连接到电源端子的第二端子。第二电容器大大降低了频率相关的谐波失真。

93. 发明授权

US07345528B2 Method and apparatus for improved clock preamplifier with low jitter 有权
标题翻译：具有低抖动的改进型时钟前置放大器的方法和装置
公开(公告)号：US07345528B2
公开(公告)日：2008-03-18
申请号：US11125960
申请日：2005-05-10
申请人： Alfio Zanchi , Marco Corsi
发明人： Alfio Zanchi , Marco Corsi
IPC分类号： G06G7/12 , H03F3/16
CPC分类号： H03F3/4517 , H03F3/42 , H03F3/4508
摘要： A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode clamper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the clamper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode clamper circuits. Preferably, MOSFET transistors of the reference voltage source and MOSFET transistors of like kind of the inverter are configured to have substantially identical threshold voltages.
摘要翻译：时钟信号前置放大器包括互补的差分耦合晶体管对，其中耦合到反相器的输出信号还包括互补MOSFET晶体管的图腾柱布置。前置放大器的输入信号通常是正弦波，输出信号是矩形的。优选地，差分耦合的晶体管是双极的，并且具有双极晶体管的一对二极管钳位电路优选地耦合到互补的差分耦合晶体管对。参考电压源耦合到钳位晶体管的控制端。优选地包括具有其输出节点的互补MOSFET晶体管的图腾柱布置的参考电压源耦合到其输入节点，为二极管钳位电路提供参考电压。优选地，参考电压源的MOSFET晶体管和类似类型的反相器的MOSFET晶体管被配置为具有基本相同的阈值电压。

94. 发明申请

US20070040580A1 Reference buffer with improved drift 有权
标题翻译：参考缓冲区具有改善的漂移
公开(公告)号：US20070040580A1
公开(公告)日：2007-02-22
申请号：US11206406
申请日：2005-08-18
申请人： Alfio Zanchi , Marco Corsi
发明人： Alfio Zanchi , Marco Corsi
IPC分类号： H03K19/094
CPC分类号： G05F3/222 , H03F1/26 , H03F1/34 , H03F3/005 , H03F3/45475 , H03F2200/372 , H03F2200/453 , H03F2203/45134 , H03F2203/45136 , H03F2203/45512 , H03F2203/45628 , H03F2203/45722
摘要： A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on the voltage reference lines. The reference voltage circuit may be adapted for a switched capacitor ADC.
摘要翻译：具有由包含在闭环中的匹配缓冲器驱动的开环缓冲器的参考电压电路产生稳定的差分或单端电压，同时最小化信号相关的短期和长期漂移。开环缓冲器可以是闭环缓冲器的复制品，减少耦合在电压参考线上的信号的影响。参考电压电路可以适用于开关电容器ADC。

95. 发明授权

US07177418B2 Power efficient ADSL central office downstream class G power switch 有权
标题翻译：高效的ADSL中心局下游G级电源开关
公开(公告)号：US07177418B2
公开(公告)日：2007-02-13
申请号：US10200459
申请日：2002-07-22
申请人： Kenneth George Maclean , Marco Corsi
发明人： Kenneth George Maclean , Marco Corsi
IPC分类号： H04M1/00 , H04M3/00
CPC分类号： H04M19/005
摘要： Systems and methods are provided for switching between power supply rail voltages for a differential driver device of a class G amplifier device. The amplifier device employs power MOSFETs to switch between supplying high supply voltages and low supply voltages to the power rails of the differential driver. The class G amplifier can be employed in driving an ADSL signal over a telephone line. A control device ramps the power supply rail voltage between low power supply states and high power supply states to mitigate noise and spikes that can be coupled to the output signal.
摘要翻译：提供了用于在G类放大器装置的差分驱动器装置的电源轨电压之间切换的系统和方法。放大器装置使用功率MOSFET来在差分驱动器的电源轨提供高电源电压和低电源电压之间切换。 G类放大器可以用于通过电话线驱动ADSL信号。控制装置在低电源状态和高电源状态之间斜坡上的电源轨电压以减轻可耦合到输出信号的噪声和尖峰。

96. 发明授权

US07009549B1 Switched-capacitor circuit with scaled reference voltage 有权
标题翻译：具有缩放参考电压的开关电容电路
公开(公告)号：US07009549B1
公开(公告)日：2006-03-07
申请号：US11026673
申请日：2004-12-30
申请人： Marco Corsi
发明人： Marco Corsi
IPC分类号： H03M1/38
CPC分类号： H03M1/08 , H03M1/0695 , H03M1/442
摘要： A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC (28) performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier (29). Sample capacitors (C10, C20) and reference capacitors (C122, C222) receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors (C121, C221) are provided to maintain constant circuit gain. Extended reference voltages (VREFPX, VREFNX) at levels that exceed the output range (V0+, V0−) of the operational amplifier (29) are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors (C12, C22) are scaled according to the extent to which the extended reference voltages (VREFPX, VREFNX) exceed the op amp output levels (V0+, V0−). The effects of noise on the reference voltages (VREFPX, VREFNX) on the residue signal (RES) are thus greatly reduced.
摘要翻译：公开了一种具有改进精度的流水线模数转换器（ADC）（30）。流水线ADC（30）包括一系列级（20），每个级包括采样保持电路（22），模数转换器（23），以及数模转换器模拟转换器（DAC）（25），加法器（24）和增益级（27），在所述增益级（27）中产生用于按顺序施加到下一级（20）的残留信号（RES）。乘法DAC（28）在级（20）中执行DAC（25），加法器（24）和增益级（27）的功能，并且基于运算放大器（29）。采样电容器（C 10，C 20）和参考电容器（C 12 2 C 22 N 2）从采样保持电路（22）接收模拟输入，在样品阶段; 提供并联电容器（C 12 1 C 22 N 2）以保持恒定的电路增益。扩展的参考电压（V SUB REFPX， REFNX）在超过输出范围（V 0> 0，V 0 响应于其阶段（20）中的模数转换器（23）的数字输出，将运算放大器（29）的“SUB” - ）施加到参考电容器。参考电容器（C 12，C 22）根据扩展的参考电压（V SUB REFXX，V REF REF）与运算放大器的输出电平 V 0，+ 0，V 0 - ）。因此，残留信号（RES）上的噪声对参考电压（V SUB REFPX，V REF REF）的影响大大降低。

97. 发明授权

US06741129B1 Differential amplifier slew rate boosting scheme 有权
标题翻译：差分放大器转换速率提升方案
公开(公告)号：US06741129B1
公开(公告)日：2004-05-25
申请号：US10324271
申请日：2002-12-19
申请人： Marco Corsi , James R. Hellums
发明人： Marco Corsi , James R. Hellums
IPC分类号： H03F345
CPC分类号： H03F3/45094 , H03F2200/153 , H03F2203/45028 , H03F2203/45546 , H03F2203/45594 , H03F2203/45601 , H03F2203/45631 , H03F2203/45632 , H03F2203/45722
摘要： A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the compensation capacitors 50 and 52 conventionally coupled to internal high impedance gain nodes 40 and 42, but has the other plates of the compensation capacitors 50 and 52 unconventionally driven with the input signal IN+ and IN−. The voltages appearing across the compensation capacitors 50 and 52 in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plates of the compensation capacitors are coupled to ground. Since little current is now required to charge the compensation capacitors 50 and 52, the input stage tail current no longer limits the slew rate.
摘要翻译：与具有非常接近1或更小的闭环增益的放大器一起使用的全差分放大器转换速率升压方案具有常规耦合到内部高阻抗增益节点40和42的补偿电容器50和52的第一板，但是具有补偿电容器50和52的其他板通过输入信号IN +和IN-非常规地驱动。响应于输入信号的变化而出现在补偿电容器50和52两端的电压显着小于使用常规补偿架构实现的电压，其中补偿电容器的其它板耦合到地。由于现在需要很少的电流来对补偿电容器50和52充电，所以输入级尾部电流不再限制压摆率。

98. 发明授权

US06614310B2 Zero-overhead class G amplifier with threshold detection 有权
标题翻译：零开销级G放大器，具有阈值检测
公开(公告)号：US06614310B2
公开(公告)日：2003-09-02
申请号：US10001330
申请日：2001-10-31
申请人： James Donald Quarfoot , Marco Corsi , Richard Knight Hester , Kenneth George Maclean
发明人： James Donald Quarfoot , Marco Corsi , Richard Knight Hester , Kenneth George Maclean
IPC分类号： H03G320
CPC分类号： H03F1/025
摘要： The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal (12) being transmitted by the line driver (20) requires it as determined by a comparator (18). Advantageously, this reduces the power dissipation in the line driver (10) by operating the line amplifier (20) the majority of the time from the lower supply voltage. A delay circuit (14) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.
摘要翻译：本发明提供了一种用于仅在信号（12）的振幅为（1）的情况下才从较低的一组电源电压和较高的一组电压来操作线路驱动器电路（10）的驱动放大器（20）的装置和方法由线路驱动器（20）传输，由比较器（18）确定。有利地，这通过在大部分时间从较低的电源电压操作线路放大器（20）来降低线路驱动器（10）中的功率消耗。延迟电路（14）将要放大的信号足够延迟以允许提供给该电源电压切换的放大器滞后的电源电压的转换也可用于进一步降低功耗。

99. 发明授权

US06535063B1 Drive method for a cross-connected class AB output stage with shared base current in pre-driver 有权
标题翻译：交流连接AB类输出级的驱动方法，具有预驱动器中的共享基极电流
公开(公告)号：US06535063B1
公开(公告)日：2003-03-18
申请号：US10005112
申请日：2001-12-03
申请人： Neil Gibson , Marco Corsi , Tobin Hagan
发明人： Neil Gibson , Marco Corsi , Tobin Hagan
IPC分类号： H03F318
CPC分类号： H03F1/307 , H03F3/3076
摘要： The present invention provides technical advantages as a class AB output driver (400) with minimal cross-over distortion. If the differential input to the driver is I+&dgr;I/2 and I−&dgr;I/2, then the current gain is the average of &bgr;n and &bgr;p, more specifically, (&bgr;n−&bgr;p)*I+((&bgr;n+&bgr;p)/2)* &dgr;I. The offset current (&bgr;n−&bgr;p)*I is taken out with a feedback loop.
摘要翻译：本发明提供了具有最小交叉失真的AB类输出驱动器（400）的技术优点。如果驱动器的差分输入为I +δI/ 2和I-δI/ 2，则当前增益是betan和betap的平均值，更具体地说，（betan-betap）* I +（（betan + betap）/ 2 ）* deltaI。偏移电流（betan-betap）* I用反馈回路取出。

100. 发明授权

US06501334B1 Actively biased class AB output stage with low quiescent power, high output current drive and wide output voltage swing 有权
标题翻译：具有低静态功率，高输出电流驱动和宽输出电压摆幅的积极偏置AB类输出级
公开(公告)号：US06501334B1
公开(公告)日：2002-12-31
申请号：US09711767
申请日：2000-11-13
申请人： Marco Corsi , Kenneth G. Maclean
发明人： Marco Corsi , Kenneth G. Maclean
IPC分类号： H03F326
CPC分类号： H03F3/3076
摘要： A class ‘AB’ amplifier output stage has an active current bias source that provides base drive current to the output transistors that is proportional to the signal input voltage level. The output transistor currents are modulated with the input signal such that the quiescent supply current is reduced to a very small level.
摘要翻译： “AB”级放大器输出级有一个有源电流偏置源，为输出晶体管提供基准驱动电流，该输出晶体管与信号输入电压电平成比例，输出晶体管电流用输入信号调制，使得静态电源电流为降至非常小的水平。

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