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91. 发明授权

US06214737B1 Simplified sidewall formation for sidewall patterning of sub 100 nm structures 失效
标题翻译：亚100 nm结构的侧壁图案的简化侧壁形成
公开(公告)号：US06214737B1
公开(公告)日：2001-04-10
申请号：US09234379
申请日：1999-01-20
申请人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
发明人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L213065
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/32139 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在导电膜的第一部分上图案化掩模，其中导电膜的第二部分被暴露; 部分蚀刻导电膜的第二部分，从而在导电膜中形成侧壁; 去除面膜; 在所述导电膜上沉积侧壁膜，所述侧壁膜具有邻近所述导电膜的侧壁的垂直部分和在不邻近所述导电膜的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 并且蚀刻导电膜的第三部分，从而提供具有在侧壁膜的垂直部分下方的约100nm或更小的宽度的导电结构。

92. 发明授权

US06196734B1 CD uniformity by active control of developer temperature 有权
标题翻译：通过主动控制显影剂温度的CD均匀性
公开(公告)号：US06196734B1
公开(公告)日：2001-03-06
申请号：US09410955
申请日：1999-10-05
申请人： Michael K. Templeton , Bharath Rangarajan
发明人： Michael K. Templeton , Bharath Rangarajan
IPC分类号： G03D500
CPC分类号： G03D13/006
摘要： A system for regulating temperature of a developer is provided. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the developer. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the developer. The measuring system provides developer temperature related data to a processor which determines the temperature of the respective portions of the developer. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the developer.
摘要翻译：提供了一种用于调节显影剂温度的系统。该系统包括多个光纤，每个光纤将辐射引导到显影剂的相应部分。从相应部分反射的辐射由处理收集的辐射的测量系统收集。反射的辐射表示显影剂各部分的温度。测量系统将显影剂温度相关数据提供给确定显影剂各部分的温度的处理器。该系统还包括多个加热装置; 每个加热装置对应于显影剂的相应部分并提供其加热。处理器选择性地控制加热装置，以便调节显影剂各部分的温度。

93. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

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