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91. 发明申请

US20060113592A1 Robust DEMOS transistors and method for making the same 有权
公开(公告)号：US20060113592A1
公开(公告)日：2006-06-01
申请号：US11325165
申请日：2006-01-04
申请人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
发明人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

92. 发明授权

US07045903B2 Integrated power circuits with distributed bonding and current flow 有权
公开(公告)号：US07045903B2
公开(公告)日：2006-05-16
申请号：US09917419
申请日：2001-07-30
申请人： Taylor R. Efland , Sameer Pendharkar
发明人： Taylor R. Efland , Sameer Pendharkar
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/48 , H01L23/4952 , H01L23/49562 , H01L23/5286 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/49 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05187 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/4554 , H01L2224/45669 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4845 , H01L2224/48463 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/49111 , H01L2224/49113 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01037 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/30105 , H01L2924/00014 , H01L2924/01007 , H01L2924/04953 , H01L2924/00 , H01L2224/48869 , H01L2924/20755 , H01L2924/00015 , H01L2924/2075
摘要： A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery between a selected pad and one or more corresponding active components, to which the power is to be delivered. This minimum distance further enhances dissipation of thermal energy released by the active components.More specifically, a semiconductor integrated circuit comprises a laterally organized power transistor, an array of power supply contact pads distributed over the transistor, means for providing a distributed, predominantly vertical current flow from the contact pads to the transistor, and means for connecting a power source to each of the contact pads. Positioning the power supply contact pads directly over the active power transistor further saves precious silicon real estate area. The means for vertical current flow include contact pads made of a stack of metal layers comprising refractory metals for adhesion, copper and nickel as stress-absorbing metals, and gold or palladium as bondable and solderable outermost metals. The means for connecting a power source include wire bonding and solder ball interconnection.

93. 发明授权

US07005354B2 Depletion drain-extended MOS transistors and methods for making the same 有权
标题翻译：消耗漏极扩展MOS晶体管及其制造方法
公开(公告)号：US07005354B2
公开(公告)日：2006-02-28
申请号：US10669111
申请日：2003-09-23
申请人： Shanjen Pan , James R. Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
发明人： Shanjen Pan , James R. Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1033 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/7835
摘要： Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
摘要翻译：提供消耗漏极扩展MOS晶体管器件及其制造方法，其中补偿沟道区域设置有p型和n型掺杂剂以便于在Vgs = 0时耗尽操作，并且将调整区域注入到衬底中厚栅电介质结构的通道侧端用于提高击穿电压额定值。补偿通道区域由n阱和p阱的重叠植入物形成，并且使用具有暴露调整区域的掩模的Vt调整植入物形成调整区域。

94. 发明申请

US20060001102A1 Drain-extended MOS transistors and methods for making the same 有权
公开(公告)号：US20060001102A1
公开(公告)日：2006-01-05
申请号：US10880907
申请日：2004-06-30
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L31/113 , H01L31/119 , H01L31/062 , H01L29/94 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

95. 发明授权

US06395593B1 Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration 有权
标题翻译：制造高端和低端保护环的方法，用于H桥结构中最低的寄生性能
公开(公告)号：US06395593B1
公开(公告)日：2002-05-28
申请号：US09550746
申请日：2000-04-17
申请人： Sameer Pendharkar , Taylor R. Efland
发明人： Sameer Pendharkar , Taylor R. Efland
IPC分类号： H01L218238
CPC分类号： H01L29/7835 , H01L21/761 , H01L29/1087
摘要： A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopant and antimony as the n-type dopant.
摘要翻译：一种使MOS器件中的寄生效应最小化的方法，其由MOS器件和器件内的双极晶体管形成，主要用于多相桥式电路。对于低侧装置，提供具有第一导电类型的衬底，其上具有相反导电类型的第一掩埋层。第一导电类型的第二掩埋层形成在第一掩埋层上，并且第二导电类型的另一层形成在第二掩埋层上。形成了延伸穿过另一层到第一掩埋层的沉降片，以将第二掩埋层和另外的层与衬底隔离。在包括源极，漏极和栅极区域的另外的层中形成MOS器件，并且沉降片连接到器件的源极端子。第二掩埋层通过将p型掺杂剂和n型掺杂剂与其中一种具有比另一种扩散速率更高的扩散速率的掺杂剂或通过首先注入和扩散两种掺杂剂之一形成一层形成，然后植入和扩散另一种掺杂剂以形成第二层。优选的掺杂剂是作为p型掺杂剂的硼和作为n型掺杂剂的锑。

96. 发明授权

US08592900B2 Drain extended CMOS with counter-doped drain extension 有权
标题翻译：漏极扩展扩展CMOS
公开(公告)号：US08592900B2
公开(公告)日：2013-11-26
申请号：US13288690
申请日：2011-11-03
申请人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
发明人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
IPC分类号： H01L21/00
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译：一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

97. 发明申请

US20120100679A1 THICK GATE OXIDE FOR LDMOS AND DEMOS 有权
标题翻译：用于LDMOS和DEMOS的厚栅氧化物
公开(公告)号：US20120100679A1
公开(公告)日：2012-04-26
申请号：US13274698
申请日：2011-10-17
申请人： Seetharaman Sridhar , Sameer Pendharkar
发明人： Seetharaman Sridhar , Sameer Pendharkar
IPC分类号： H01L21/8238
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.
摘要翻译：一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物或LDMOS晶体管。一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物，另一个栅介质层，并保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。

98. 发明授权

US08148228B2 Surface patterned topography feature suitable for planarization 有权
标题翻译：表面图案形貌特征适用于平坦化
公开(公告)号：US08148228B2
公开(公告)日：2012-04-03
申请号：US11696829
申请日：2007-04-05
申请人： Sameer Pendharkar , Binghua Hu , Xinfen Celia Chen
发明人： Sameer Pendharkar , Binghua Hu , Xinfen Celia Chen
IPC分类号： H01L21/8228
CPC分类号： H01L29/7322 , H01L23/544 , H01L29/41708 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.
摘要翻译：一种用于制造半导体器件的方法，包括在衬底的阱区中注入第一掺杂剂类型以形成由所述阱区的非植入区域分离的注入的子区。该方法还包括在阱区上形成氧化物层，使得注入的子区域的氧化物转化的第一厚度大于非植入区域的氧化物转化的第二厚度。该方法还包括去除氧化物层以在阱区上形成形貌特征。地形特征包括较高和较低部分的表面图案。更高的部分对应于非植入区域的位置，并且下部对应于植入的子区域。

99. 发明授权

US08124482B2 MOS transistor with gate trench adjacent to drain extension field insulation 有权
标题翻译： MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻
公开(公告)号：US08124482B2
公开(公告)日：2012-02-28
申请号：US13006589
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

100. 发明授权

US07943472B2 CoSi2 Schottky diode integration in BiSMOS process 有权
标题翻译： CoSi2肖特基二极管整合在BiSMOS工艺中
公开(公告)号：US07943472B2
公开(公告)日：2011-05-17
申请号：US12023190
申请日：2008-01-31
申请人： Sameer Pendharkar , Eugen Pompiliu Mindricelu
发明人： Sameer Pendharkar , Eugen Pompiliu Mindricelu
IPC分类号： H01L21/329 , H01L21/20
CPC分类号： H01L27/0814 , H01L21/8249 , H01L27/0635 , H01L29/0619 , H01L29/47 , H01L29/872
摘要： Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation.
摘要翻译：根据当前技术制造的硅化硅（CoSi 2）肖特基二极管在反向偏压下遭受过量的漏电流。在本发明中，浮动p型区域包围由一个或多个CoSi 2阳极组成的CoSi 2肖特基二极管的每个阳极。所得的p-n结在肖特基结下形成耗尽区，在反向偏压操作中减少穿过肖特基二极管的漏电流。

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