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91. 发明申请

US20050122801A1 Flexible row redundancy system 有权
标题翻译：灵活的行冗余系统
公开(公告)号：US20050122801A1
公开(公告)日：2005-06-09
申请号：US11031138
申请日：2005-01-07
申请人： Louis Hsu , Gregory Fredeman , Rajiv Joshi , Toshiaki Kirihata
发明人： Louis Hsu , Gregory Fredeman , Rajiv Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. Furthermore, a method is provided for replacing faulty wordlines of a memory array including the steps of: selecting a repair field size; storing at least one faulty address into a first memory; and copying the stored at least one faulty address from the first memory into a variable number of storage cells of a second memory, wherein each storage cell of said second memory corresponds to a respective bank of said plurality of banks; and wherein the variable number of storage cells is in accordance with the selected repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。此外，提供了一种用于替换存储器阵列的错误字线的方法，包括以下步骤：选择修复字段大小; 将至少一个故障地址存储到第一存储器中; 以及将存储的至少一个故障地址从第一存储器复制到第二存储器的可变数量的存储单元中，其中所述第二存储器的每个存储单元对应于所述多个存储体的相应存储体; 并且其中所述可变数量的存储单元符合所选择的修复字段大小。

92. 发明申请

US20050106800A1 CMOS well structure and method of forming the same 有权
标题翻译： CMOS阱结构及其形成方法
公开(公告)号：US20050106800A1
公开(公告)日：2005-05-19
申请号：US10713447
申请日：2003-11-14
申请人： Wilfried Haensch , Terence Hook , Louis Hsu , Rajiv Joshi , Werner Rausch
发明人： Wilfried Haensch , Terence Hook , Louis Hsu , Rajiv Joshi , Werner Rausch
IPC分类号： H01L21/76 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823892 , H01L27/0928
摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.
摘要翻译：一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。在每个第一导电类型的阱上形成盖，并且去除第一掩模。在每个第一导电类型的孔的侧壁上形成侧壁间隔物。形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

93. 发明授权

US06570434B1 Method to improve charge pump reliability, efficiency and size 失效
公开(公告)号：US06570434B1
公开(公告)日：2003-05-27
申请号：US09662685
申请日：2000-09-15
申请人： Louis Hsu , Russell J. Houghton , Oliver Weinfurtner
发明人： Louis Hsu , Russell J. Houghton , Oliver Weinfurtner
IPC分类号： G05F302
CPC分类号： G11C5/145
摘要： A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

94. 发明授权

US06524908B2 Method for forming refractory metal-silicon-nitrogen capacitors and structures formed 失效
$Method for forming refractory metal-silicon-nitrogen capacitors and structures formed$
标题翻译：形成难熔金属 - 硅 - 氮电容器和结构的方法
公开(公告)号：US06524908B2
公开(公告)日：2003-02-25
申请号：US09872603
申请日：2001-06-01
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
IPC分类号： H01L218242
CPC分类号： H01L28/75 , C23C14/0073 , C23C14/0641 , H01L21/2855 , H01L21/28568
摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.
摘要翻译：描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。在该方法中，首先将预处理的半导体衬底定位在溅射室中。然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

95. 发明授权

US08024012B2 Intelligent wireless power charging system 有权
标题翻译：智能无线充电系统
公开(公告)号：US08024012B2
公开(公告)日：2011-09-20
申请号：US12137185
申请日：2008-06-11
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
IPC分类号： H04B1/38 , H04B1/16
CPC分类号： H02J50/20 , H02J7/025 , H02J17/00
摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.
摘要翻译：一种用于无线网络设备智能电源管理的系统和方法。该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。电池通过嵌入在无线设备内部的射频收集单元进行充电。智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。第一个适配器设置为数据通信，而第二个适配器用于传输电源。此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

96. 发明授权

US07851321B2 Semiconductor integrated circuit devices having high-Q wafer back-side capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US07851321B2
公开(公告)日：2010-12-14
申请号：US12348707
申请日：2009-01-05
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

97. 发明授权

US07486114B2 Signal detector with calibration circuit arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US07486114B2
公开(公告)日：2009-02-03
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K5/19
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：一种用于检测输入差分信号的存在或不存在的信号检测器和方法。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

98. 发明申请

US20080108220A1 INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE 有权
标题翻译：具有障碍 - 冗余特征的互连结构
公开(公告)号：US20080108220A1
公开(公告)日：2008-05-08
申请号：US11925161
申请日：2007-10-26
申请人： Chih-Chao Yang , Louis Hsu
发明人： Chih-Chao Yang , Louis Hsu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.
摘要翻译：提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

99. 发明申请

US20080068038A1 Systems and Methods for Controlling of Electro-Migration 有权
公开(公告)号：US20080068038A1
公开(公告)日：2008-03-20
申请号：US11942241
申请日：2007-11-19
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

100. 发明申请

US20080050890A1 HYBRID ORIENTED SUBSTRATES AND CRYSTAL IMPRINTING METHODS FOR FORMING SUCH HYBRID ORIENTED SUBSTRATES 失效
标题翻译：用于形成这种混合基板的混合基板和晶体印刷方法
公开(公告)号：US20080050890A1
公开(公告)日：2008-02-28
申请号：US11928456
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
摘要翻译：一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。体硅区域各自定向为具有第三晶体取向。还提供了形成SOI区域和体硅区域的镶嵌或印刷方法。

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