专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20080215943A1 Generating test sets for diagnosing scan chain failures 有权
标题翻译：生成用于诊断扫描链故障的测试集
公开(公告)号：US20080215943A1
公开(公告)日：2008-09-04
申请号：US12074162
申请日：2008-02-29
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/318533 , G01R31/318544 , G01R31/318569
摘要： Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
摘要翻译：所公开的技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。这样的实施例可用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。

92. 发明申请

US20070281156A1 Nanoscale wires and related devices 审中-公开
公开(公告)号：US20070281156A1
公开(公告)日：2007-12-06
申请号：US11386080
申请日：2006-03-21
申请人： Charles Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David Smith , Deli Wang , Zhaohui Zhong
发明人： Charles Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David Smith , Deli Wang , Zhaohui Zhong
IPC分类号： D02G3/00
CPC分类号： G11C13/025 , B82Y10/00 , B82Y15/00 , B82Y30/00 , C30B11/00 , C30B25/00 , C30B25/005 , C30B29/60 , C30B29/605 , G01N27/4146 , G01N33/54373 , G11C11/56 , G11C13/0014 , G11C13/0019 , G11C13/04 , G11C2213/17 , G11C2213/18 , G11C2213/77 , G11C2213/81 , H01L21/02532 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/02557 , H01L21/0256 , H01L21/02603 , H01L21/02617 , H01L21/02628 , H01L21/02645 , H01L21/02653 , H01L23/53276 , H01L27/092 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L29/1606 , H01L29/2003 , H01L29/207 , H01L29/267 , H01L29/73 , H01L29/7781 , H01L29/78696 , H01L29/861 , H01L29/868 , H01L31/0352 , H01L31/08 , H01L33/18 , H01L51/0048 , H01L51/0595 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , Y02E10/549 , Y10S977/936 , Y10S977/938 , Y10S977/958 , Y10T428/2929 , Y10T428/298 , H01L2924/00
摘要： The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

93. 发明授权

US07301199B2 Nanoscale wires and related devices 有权
标题翻译：纳米线及相关设备
公开(公告)号：US07301199B2
公开(公告)日：2007-11-27
申请号：US10196337
申请日：2002-07-16
申请人： Charles M. Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln J. Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David C. Smith , Deli Wang , Zhaohui Zhong
发明人： Charles M. Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln J. Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David C. Smith , Deli Wang , Zhaohui Zhong
IPC分类号： H01L29/76 , H01L29/94 , H01L29/06
CPC分类号： G11C13/025 , B82Y10/00 , B82Y15/00 , B82Y30/00 , C30B11/00 , C30B25/00 , C30B25/005 , C30B29/60 , C30B29/605 , G01N27/4146 , G01N33/54373 , G11C11/56 , G11C13/0014 , G11C13/0019 , G11C13/04 , G11C2213/17 , G11C2213/18 , G11C2213/77 , G11C2213/81 , H01L21/02532 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/02557 , H01L21/0256 , H01L21/02603 , H01L21/02617 , H01L21/02628 , H01L21/02645 , H01L21/02653 , H01L23/53276 , H01L27/092 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L29/1606 , H01L29/2003 , H01L29/207 , H01L29/267 , H01L29/73 , H01L29/7781 , H01L29/78696 , H01L29/861 , H01L29/868 , H01L31/0352 , H01L31/08 , H01L33/18 , H01L51/0048 , H01L51/0595 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , Y02E10/549 , Y10S977/936 , Y10S977/938 , Y10S977/958 , Y10T428/2929 , Y10T428/298 , H01L2924/00
摘要： The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.
摘要翻译：本发明一般涉及亚微电子电路，更具体地涉及纳米尺度制品，包括可以在各种位置和各种级别选择性地掺杂的纳米线。在一些情况下，制品可以是单晶。纳米尺寸线可以例如沿其长度或径向掺杂，或者根据掺杂剂的掺杂剂浓度，掺杂剂的浓度或两者掺杂。这可以用于在单个项目中提供n型和p型导电性，或者在彼此非常接近的不同项目中提供，例如在横杆阵列中。描述了这种制品的制造和生长，以及这些制品的布置以制造电子，光电子或自旋电子器件和部件。例如，可以掺杂半导体材料以形成n型和p型半导体区域，用于制造诸如场效应晶体管，双极晶体管，互补反相器，隧道二极管，发光二极管，传感器等的各种器件。

94. 发明授权

US07254151B2 Nanoscale coherent optical components 有权
标题翻译：纳米级相干光学元件
公开(公告)号：US07254151B2
公开(公告)日：2007-08-07
申请号：US10734086
申请日：2003-12-11
申请人： Charles M. Lieber , Xiangfeng Duan , Yu Huang , Ritesh Agarwal
发明人： Charles M. Lieber , Xiangfeng Duan , Yu Huang , Ritesh Agarwal
IPC分类号： H01S5/00
CPC分类号： G11C13/025 , B82Y10/00 , B82Y20/00 , B82Y30/00 , G11C2213/17 , G11C2213/18 , H01S5/021 , H01S5/10 , H01S5/12 , H01S5/20 , H01S5/341 , H01S5/343 , H01S5/347 , Y10S977/825 , Y10S977/951
摘要： This invention generally relates to nanotechnology and nanoelectronics as well as associated methods and devices. In particular, the invention relates to nanoscale optical components such as electroluminescence devices (e.g., LEDs), amplified stimulated emission devices (e.g., lasers), waveguides, and optical cavities (e.g., resonators). Articles and devices of a size greater than the nanoscale are also included. Such devices can be formed from nanoscale wires such as nanowires or nanotubes. In some cases, the nanoscale wire is a single crystal. In one embodiment, the nanoscale laser is constructed as a Fabry-Perot cavity, and is driven by electrical injection. Any electrical injection source may be used. For example, electrical injection may be accomplished through a crossed wire configuration, an electrode or distributed electrode configuration, or a core/shell configuration. The output wavelength can be controlled, for example, by varying the types of materials used to fabricate the device. One or more such nanoscale lasers may also be integrated with other nanoscale components within a device.
摘要翻译：本发明一般涉及纳米技术和纳米电子学以及相关的方法和装置。特别地，本发明涉及纳米尺度光学部件，例如电致发光器件（例如，LED），放大的受激发射器件（例如，激光器），波导和光学腔（例如谐振器）。还包括尺寸大于纳米尺寸的物品和装置。这样的器件可以由诸如纳米线或纳米管的纳米尺寸线形成。在某些情况下，纳米线是单晶。在一个实施例中，纳米级激光器被构造为法布里 - 珀罗腔，并且通过电注入驱动。可以使用任何电喷射源。例如，电注入可以通过交叉线配置，电极或分布电极配置或核/壳配置来实现。可以例如通过改变用于制造器件的材料的类型来控制输出波长。一个或多个这样的纳米尺度激光器也可以与器件内的其他纳米级组件集成。

95. 发明授权

US07254028B2 Heat dissipating device with back plate for electronic assembly 失效
标题翻译：散热装置，带背板用于电子组装
公开(公告)号：US07254028B2
公开(公告)日：2007-08-07
申请号：US11269379
申请日：2005-11-08
申请人： Hsieh-Kun Lee , Chun-Chi Chen , Shin-Hsuu Wung , Yu Huang
发明人： Hsieh-Kun Lee , Chun-Chi Chen , Shin-Hsuu Wung , Yu Huang
IPC分类号： H05K7/20
CPC分类号： H01L23/4093 , H01L2924/0002 , H01L2924/00
摘要： An electronic assembly includes a PCB (20), a socket (22) mounted on the PCB, a CPU (24) connected with the socket, a heat sink (10) in thermal contact with the CPU, a foldable back plate (30) attached to an underside of the PCB and a base plane (40) forming four bridges (42). The back plate includes a first piece section (32) and a second piece section (34) pivotally joined together by a pivot (36). The first and the second piece sections each comprise two legs inserted into two corresponding bridges. Screws are used to extend through the heat sink, the PCB, the bridges to threadedly engage with the legs of the back plate, respectively. The pivot is located under a part of the PCB at which the CPU is mounted.
摘要翻译：电子组件包括PCB（20），安装在PCB上的插座（22），与插座连接的CPU（24），与CPU热接触的散热器（10），可折叠背板（30）附接到PCB的下侧和形成四个桥（42）的基面（40）。后板包括通过枢轴（36）枢轴连接在一起的第一片段（32）和第二片段（34）。第一和第二片段各自包括插入到两个对应的桥中的两个腿。螺丝用于延伸穿过散热片，PCB，桥接件分别与背板的腿部螺纹接合。枢轴位于安装有CPU的PCB的一部分下方。

96. 发明申请

US20070048492A1 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices 有权
公开(公告)号：US20070048492A1
公开(公告)日：2007-03-01
申请号：US11543337
申请日：2006-10-04
申请人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
发明人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
IPC分类号： B32B5/00
CPC分类号： H01L29/0665 , B01J23/50 , B01J23/52 , B01J23/72 , B01J35/0013 , B01J37/349 , B81C1/0019 , B81C1/00206 , B82Y10/00 , B82Y15/00 , B82Y30/00 , B82Y40/00 , C30B11/00 , C30B25/005 , C30B29/605 , G01N27/4146 , G01N33/54373 , G11C13/0014 , G11C13/0019 , G11C13/025 , G11C13/04 , G11C2213/77 , G11C2213/81 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/02543 , H01L21/02557 , H01L21/0256 , H01L21/02573 , H01L21/02581 , H01L21/02603 , H01L21/02606 , H01L21/0262 , H01L21/02628 , H01L21/02631 , H01L21/02636 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L23/53276 , H01L29/045 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/1602 , H01L29/18 , H01L29/20 , H01L29/207 , H01L29/22 , H01L29/24 , H01L29/26 , H01L29/267 , H01L33/06 , H01L33/18 , H01L33/20 , H01L51/002 , H01L51/0048 , H01L2924/0002 , Y02E10/549 , Y02P70/521 , Y10S438/962 , Y10S977/762 , Y10S977/847 , Y10S977/858 , Y10S977/882 , Y10S977/883 , Y10S977/892 , Y10S977/936 , Y10T428/24 , H01L2924/00
摘要： A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

97. 发明申请

US20060279918A1 PROTECTION MECHANISM FOR CONNECTORS 失效
标题翻译：连接器保护机构
公开(公告)号：US20060279918A1
公开(公告)日：2006-12-14
申请号：US11306452
申请日：2005-12-29
申请人： Shu-Gang Shi , Yu Huang
发明人： Shu-Gang Shi , Yu Huang
IPC分类号： G06F1/16
CPC分类号： G06F1/181
摘要： A protection mechanism in accordance with a preferred embodiment of the present invention includes a bracket for being secured to a rear portion of a computer chassis, and first and second covers respectively pivotally attached to the bracket. Adjacent sides of the first and second covers each form a lug. The lug of the first cover abuts against the lug of the second cover so as to prevent the second cover from rotating.
摘要翻译：根据本发明的优选实施例的保护机构包括用于固定到计算机机箱的后部的支架，以及分别枢转地附接到支架的第一和第二盖。第一和第二盖的相邻侧各自形成凸耳。第一盖的凸耳抵靠第二盖的凸耳，以防止第二盖旋转。

98. 发明授权

US06934897B2 Scheduling the concurrent testing of multiple cores embedded in an integrated circuit 有权
标题翻译：调度嵌入在集成电路中的多个内核的并发测试
公开(公告)号：US06934897B2
公开(公告)日：2005-08-23
申请号：US10210794
申请日：2002-07-31
申请人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
发明人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
IPC分类号： G01R31/3193 , G01R31/28
CPC分类号： G01R31/3193
摘要： Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.
摘要翻译：描述了用于调度嵌入在集成电路中的多个核的并发测试的方法。通过将问题解决为二进制包装问题并使用修改后的二维或三维二进制包装启发式来进行测试调度。多个核心的测试表示为至少用于测试核心和核心测试时间的集成电路引脚的功能。表示可以包括测试核心所需的峰值功率的第三维度。测试计划表示为具有至少集成电路引脚和集成电路测试时间的尺寸的存储区。箱可以包括峰值功率的第三维度。多核的调度是通过将多个核心测试表示拟合到bin来实现的。

99. 发明授权

US09734867B2 Media processing devices for detecting and ranking insertion points in media, and methods thereof 有权
公开(公告)号：US09734867B2
公开(公告)日：2017-08-15
申请号：US13069136
申请日：2011-03-22
申请人： Yu Huang , Chao Zhang , Hong Heather Yu , Dongjing Shan
发明人： Yu Huang , Chao Zhang , Hong Heather Yu , Dongjing Shan
IPC分类号： H04N7/10 , G11B27/031 , G11B27/28 , H04N21/233 , H04N21/234 , H04N21/845
CPC分类号： G11B27/031 , G11B27/28 , H04N21/233 , H04N21/23418 , H04N21/23424 , H04N21/8455 , H04N21/8456
摘要： In accordance with an embodiment of the present invention, a method for inserting secondary content into a media stream includes dividing the media stream having a plurality of frames into a plurality of shots at a processor. The method further includes grouping consecutive shots from the plurality of shots into a plurality of scenes. A first list of insertion points is generated for introducing the secondary content. The insertion points of the first list are boundaries between consecutive scenes in the plurality of scenes. An average insertion point saliency of the media stream is generated at the insertion points in the first list. A second list of insertion points is then generated. The insertion points in the second list are arranged to maximize a function of the average insertion point saliency and a distance between each insertion point in the second list with other insertion points in the second list.

100. 发明授权

US09342472B2 PRD (physical region descriptor) pre-fetch methods for DMA (direct memory access) units 有权
标题翻译：用于DMA（直接存储器访问）单元的PRD（物理区域描述符）预取方法
公开(公告)号：US09342472B2
公开(公告)日：2016-05-17
申请号：US11935429
申请日：2007-11-06
申请人： Peng Gao , Yu Huang , Dejian Li
发明人： Peng Gao , Yu Huang , Dejian Li
IPC分类号： G06F13/28 , G06F12/08
CPC分类号： G06F13/28 , G06F12/0875
摘要： PRD (Physical Region Descriptor) pre-fetch methods for DMA (Direct Memory Access) unit are provided. When a DMA out transaction for a memory is performed, it is determined whether a first queue is full or nearly full, wherein the first queue is used to store data corresponding to the DMA out transaction. If the first queue is full or nearly full, at least one PRD entry is read from a first PRD table, and stored to a first cache. When a DMA in transaction for the memory is performed, it is determined whether a second queue is empty or nearly empty, wherein the second queue is used to store data corresponding to the DMA in transaction. If the second queue is empty or nearly empty, at least one PRD entry is read from a second PRD table, and stored to a second cache.
摘要翻译：提供了用于DMA（直接存储器访问）单元的PRD（物理区域描述符）预取方法。当执行用于存储器的DMA输出事务时，确定第一队列是否满或已满，其中第一队列用于存储对应于DMA输出事务的数据。如果第一个队列已满或已满，则从第一个PRD表中读取至少一个PRD条目，并存储到第一个缓存。当执行用于存储器的事务中的DMA时，确定第二队列是空还是几乎为空，其中第二队列用于在事务中存储对应于DMA的数据。如果第二队列为空或几乎为空，则从第二PRD表读取至少一个PRD条目，并存储到第二高速缓存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式