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91. 发明申请

US20080107801A1 METHOD OF MAKING A VARIABLE RESISTANCE MEMORY 审中-公开
标题翻译：制造可变电阻记忆体的方法
公开(公告)号：US20080107801A1
公开(公告)日：2008-05-08
申请号：US11937481
申请日：2007-11-08
申请人： Jolanta Celinska , Carlos A. Paz de Araujo , Matthew D. Brubaker
发明人： Jolanta Celinska , Carlos A. Paz de Araujo , Matthew D. Brubaker
IPC分类号： B05D5/12
CPC分类号： H01L45/04 , G11C13/0002 , G11C2213/79 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method of making a variable resistance material (VRM), the method comprising providing a precursor comprising a metallorganic or organometallic solvent containing a metal moiety suitable for forming the VRM, depositing the precursor on a substrate to form a thin film of the precursor, and heating the thin film to form the VRM. The preferred solvent comprises octane.
摘要翻译：一种制备可变电阻材料（VRM）的方法，所述方法包括提供包含含有适于形成VRM的金属部分的金属有机或有机金属溶剂的前体，将前体沉积在基底上以形成前体的薄膜，以及加热薄膜以形成VRM。优选的溶剂包括辛烷。

92. 发明申请

US20080106926A1 NON-VOLATILE RESISTANCE SWITCHING MEMORIES AND METHODS OF MAKING SAME 有权
标题翻译：非易失性电阻开关存储器及其制造方法
公开(公告)号：US20080106926A1
公开(公告)日：2008-05-08
申请号：US11937479
申请日：2007-11-08
申请人： Matthew D. Brubaker , Carlos A. Paz de Araujo , Jolanta Celinska
发明人： Matthew D. Brubaker , Carlos A. Paz de Araujo , Jolanta Celinska
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/24 , G11C13/0007 , G11C2213/32 , G11C2213/53 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L29/685 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
摘要翻译：一种集成电路存储单元，包括：具有第一有源区，第二有源区和在有源区之间的沟道的半导体; 以及在通道正上方的可变电阻材料层（VRM）。在一个实施例中，在VRM和沟道之间存在第一导电层，以及VRM层正上方的第二导电层。 VRM优选为相关电子材料（CEM）。存储单元包括FET，例如JFET或MESFET。在另一个实施例中，在VRM和通道之间存在绝缘材料层。在这种情况下，存储单元可以包括MOSFET结构。

93. 发明授权

US06867452B2 Interlayer oxide containing thin films for high dielectric constant application of the formula AB2O6 or AB2O7 失效
标题翻译：含有氧化物的薄膜用于高介电常数应用的AB2O6或AB2O7
公开(公告)号：US06867452B2
公开(公告)日：2005-03-15
申请号：US10278581
申请日：2002-10-23
申请人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
发明人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
IPC分类号： H01L21/314 , H01L21/316 , H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02197 , H01L21/02205 , H01L21/02282 , H01L21/02348 , H01L21/31691 , H01L27/0629
摘要： A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦y≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNb1−y)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is
摘要翻译：一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜。一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0 <= y <= 1.0且0 <= Y＆LE; 1.0; （BAxSr1-x）2（TayNb1-y）2O7，其中0 <= x <= 1.0且0 <= y <= 1.0; AND（BAxSr1-x）2Bi2（TayNb1-y）2O10，其中0 <= x <= 1.0且0 <= y <= 1.0。根据本发明的薄膜的相对介电常数> 40，优选约100。本发明的金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

94. 发明授权

US06664115B2 Metal insulator structure with polarization-compatible buffer layer 有权
标题翻译：具有极化兼容缓冲层的金属绝缘体结构
公开(公告)号：US06664115B2
公开(公告)日：2003-12-16
申请号：US09899670
申请日：2001-07-05
申请人： Masamichi Azuma , Carlos A. Paz de Araujo
发明人： Masamichi Azuma , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L21/02304 , C23C16/448 , C23C16/45561 , C23C18/1216 , C23C18/1225 , C23C18/1295 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/02197 , H01L21/02282 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/60 , H01L29/78391
摘要： An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a taxis orientation to the final crystal, and results in improved thin-film electrical properties.
摘要翻译： MIS器件（20）包括半导体衬底（22），氮化硅缓冲层（24），铁电金属氧化物超晶格材料（26）和贵金属顶电极（28）。层状超晶格材料（26）优选为钽酸锶锶，铌酸铋锶或钽酸铋铌钽酸锶。根据优选的方法构造器件，其包括在沉积层状超晶格材料之前在半导体衬底上形成氮化硅。层状超晶格材料优选使用液体聚氧化烷基化的金属有机前体沉积，其在加热前体溶液时自发产生层状超晶格。在前体液体的干燥期间的紫外线暴露赋予了最终晶体的出租车方向，并且导致改善的薄膜电性能。

95. 发明授权

US06562678B1 Chemical vapor deposition process for fabricating layered superlattice materials 有权
公开(公告)号：US06562678B1
公开(公告)日：2003-05-13
申请号：US09521094
申请日：2000-03-07
申请人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

96. 发明授权

US06541279B2 Method for forming an integrated circuit 有权
标题翻译：集成电路形成方法
公开(公告)号：US06541279B2
公开(公告)日：2003-04-01
申请号：US09798310
申请日：2001-03-02
申请人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
发明人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , H01L21/02205 , H01L21/02282 , H01L21/02348 , H01L21/31691 , H01L27/0629
摘要： A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is
摘要翻译：一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜。一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0 <= x <= 1.0且0 <= y <= 1.0; （BaxSr1-x）2（TayNb1-y）2O7，其中0 <= x <= 1.0且0 <= y <= 1.0; 和（BaxSr1-x）2Bi2（TayNby-1）2O10，其中0 <= x <= 1.0且0 <= y <= 1.0。根据本发明的薄膜的相对介电常数> 40，优选约100.本发明金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

97. 发明授权

US06469334B2 Ferroelectric field effect transistor 失效
标题翻译：铁电场效应晶体管
公开(公告)号：US06469334B2
公开(公告)日：2002-10-22
申请号：US09821596
申请日：2001-03-29
申请人： Koji Arita , Shinichiro Hayashi , Tatsuo Otsuki , Carlos A. Paz de Araujo
发明人： Koji Arita , Shinichiro Hayashi , Tatsuo Otsuki , Carlos A. Paz de Araujo
IPC分类号： H01L2994
CPC分类号： H01L28/56 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.
摘要翻译：具有含有ZrO 2的界面绝缘体层的铁电FET。铁电FET包括栅极氧化物层，界面绝缘体层位于栅极氧化物层上，并且铁电层状超晶格材料位于界面绝缘体层上。界面绝缘体层的厚度为15至25纳米。

98. 发明授权

US06372286B1 Barium strontium titanate integrated circuit capacitors and process for making the same 失效
标题翻译：钛酸钡锶集成电路电容器及其制造方法
公开(公告)号：US06372286B1
公开(公告)日：2002-04-16
申请号：US08277035
申请日：1994-07-19
申请人： Masamichi Azuma , Michael C. Scott , Carlos A. Paz de Araujo , Joseph D. Cuchiaro
发明人： Masamichi Azuma , Michael C. Scott , Carlos A. Paz de Araujo , Joseph D. Cuchiaro
IPC分类号： B05D512
CPC分类号： C04B35/4682 , C04B35/6264 , C04B2235/3213 , C04B2235/3224 , C04B2235/3227 , C04B2235/3229 , C04B2235/3243 , C04B2235/3268 , C04B2235/441 , C04B2235/449 , C04B2235/72 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1275 , C23C18/14 , C30B7/00 , C30B29/68 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60
摘要： Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 2000 Å. Typical gain sizes are 40 nanometers and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and an xylene exchange is preformed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 675° C. and 850° C.
摘要翻译：集成电路电容器，其中电容器电介质是具有小于2000埃的晶粒尺寸的BST薄膜。典型的增益尺寸为40纳米以下。 BST通过旋涂工艺沉积液体前体而形成。原始液体前体包括溶解在2-甲氧基乙醇中的烷氧基羧酸酯，并且在旋转之前预先形成二甲苯交换。前体在空气中在约400℃的温度下干燥，然后在675℃至850℃的温度下在氧气中进行炉退火。

99. 发明授权

US06255121B1 Method for fabricating ferroelectric field effect transistor having an interface insulator layer formed by a liquid precursor 失效
标题翻译：具有由液体前体形成的界面绝缘体的铁电场效应晶体管的制造方法
公开(公告)号：US06255121B1
公开(公告)日：2001-07-03
申请号：US09258489
申请日：1999-02-26
申请人： Koji Arita , Shinichiro Hayashi , Tatsuo Otsuki , Carlos A. Paz de Araujo
发明人： Koji Arita , Shinichiro Hayashi , Tatsuo Otsuki , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.
摘要翻译：一种用于在铁电FET存储器中形成界面绝缘体层的方法，其中将液体前体施加到半导体衬底。优选地，液体前体是使用液体源雾化沉积技术施加的增强的金属有机分解（“EMOD”）前体。优选地，施加到基底上的EMOD前体溶液含有相对摩尔比例含有金属部分的金属乙基己酸，以形成含有ZrO 2，CeO 2，Y 2 O 3或（Ce 1-x Zr x）O 2的界面绝缘体层，其中0≤x≤1。

100. 发明授权

US06207465B1 Method of fabricating ferroelectric integrated circuit using dry and wet etching 失效
标题翻译：使用干法和湿蚀刻制作铁电集成电路的方法
公开(公告)号：US06207465B1
公开(公告)日：2001-03-27
申请号：US09062248
申请日：1998-04-17
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/32132 , H01L21/32134 , H01L21/32136 , H01L27/1085 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： In a ferroelectric integrated circuit, a hydrogen barrier layer comprising titanium or titanium nitride or both is formed over a metal oxide element to protect it from hydrogen degradation. After hydrogen annealing and other process steps causing hydrogenating or reducing conditions, the hydrogen barrier layer is removed in a two-step etching process. The first etch step is a dry etch, preferably a standard ion-mill etching process, which rapidly removes most of the hydrogen barrier layer. The second step is a wet, chemical etch, preferably using a solution containing NH4OH, H2O2, and H2O, which selectively removes remnants of the hydrogen barrier layer from the circuit by oxidizing a chemical element of the barrier layer. The metal oxide material preferably comprises a layered superlattice compound.
摘要翻译：在铁电集成电路中，在金属氧化物元件上形成包含钛或氮化钛或二者的氢阻挡层，以防止其降解氢。在氢退火和引起氢化或还原条件的其它工艺步骤之后，在两步蚀刻工艺中除去氢气阻挡层。第一蚀刻步骤是干蚀刻，优选标准离子磨蚀刻蚀工艺，其快速去除大部分氢阻挡层。第二步是湿化学蚀刻，优选使用含有NH 4 OH，H 2 O 2和H 2 O的溶液，其通过氧化阻挡层的化学元素从电路中选择性地除去氢阻挡层的残余物。金属氧化物材料优选包含层状超晶格化合物。

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