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91. 发明授权

US07958309B2 Dynamic selection of a memory access size 有权
标题翻译：动态选择内存访问大小
公开(公告)号：US07958309B2
公开(公告)日：2011-06-07
申请号：US12024476
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

92. 发明授权

US07779148B2 Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips 有权
标题翻译：基于在广播心跳信号中接收到的未响应的活动源请求数量的信息进行动态路由并存储在其他处理器芯片的本地数据结构中
公开(公告)号：US07779148B2
公开(公告)日：2010-08-17
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F15/163
CPC分类号： H04L45/122 , H04L45/06
摘要： A mechanism for performing dynamic request routing based on broadcast source request information is provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播源请求信息进行动态请求路由的机制。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

93. 发明申请

US20100070711A1 Techniques for Cache Injection in a Processor System Using a Cache Injection Instruction 有权
标题翻译：使用缓存注入指令的处理器系统中缓存注入的技术
公开(公告)号：US20100070711A1
公开(公告)日：2010-03-18
申请号：US12212935
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/061 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0835 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.
摘要翻译：用于执行高速缓存注入的技术包括响应于高速缓存注入指令监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于与高速缓存注入指令相关联的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

94. 发明申请

US20090198915A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT DYNAMICALLY SELECT A MEMORY ACCESS SIZE 有权
标题翻译：数据处理系统，处理器和动态地选择存储器访问大小的方法
公开(公告)号：US20090198915A1
公开(公告)日：2009-08-06
申请号：US12024476
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

95. 发明授权

US08024527B2 Partial cache line accesses based on memory access patterns 有权
标题翻译：基于内存访问模式的部分缓存行访问
公开(公告)号：US08024527B2
公开(公告)日：2011-09-20
申请号：US12024432
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F9/30043 , G06F9/383 , G06F12/0811 , G06F12/0831 , G06F12/0886
摘要： According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial read request that requests permission to read only the target granule of the target cache line. In response to a combined response to the partial read request indicating success, the combined response representing a system-wide response to the partial read request, the processing unit receives the target granule of the target cache line, supplies the target granule to a requesting processor core, and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the target cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于读取包含多个粒度的目标高速缓存行数据的目标颗粒的处理器请求，处理单元来源于多处理器数据处理系统a的互连部分读取请求，请求权限只读取目标缓存行的目标颗粒。响应于表示成功的部分读取请求的组合响应，表示对部分读取请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒，将目标颗粒提供给请求处理器并且在保持目标高速缓存行的至少一个其他粒子的一致性状态的同时更新目标粒子的相关性状态。

96. 发明申请

US20100070712A1 Techniques for Cache Injection in a Processor System with Replacement Policy Position Modification 失效
标题翻译：具有更换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US20100070712A1
公开(公告)日：2010-03-18
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

97. 发明申请

US20100070710A1 Techniques for Cache Injection in a Processor System 有权
标题翻译：处理器系统中缓存注入的技术
公开(公告)号：US20100070710A1
公开(公告)日：2010-03-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

98. 发明申请

US20090198957A1 System and Method for Performing Dynamic Request Routing Based on Broadcast Queue Depths 失效
标题翻译：基于广播队列深度执行动态请求路由的系统和方法
公开(公告)号：US20090198957A1
公开(公告)日：2009-08-06
申请号：US12024514
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/17
摘要： A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播深度队列信息进行动态请求路由的系统和方法。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

99. 发明申请

US20090063886A1 System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture 有权
标题翻译：在多层全图互连架构中提供集群宽系统时钟的系统
公开(公告)号：US20090063886A1
公开(公告)日：2009-03-05
申请号：US11848440
申请日：2007-08-31
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , H04J3/0685 , H04Q2213/13092 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译：提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。计算群集中的每个处理器芯片发送的心跳信号同步。基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

100. 发明授权

US08332588B2 Performing a partial cache line storage-modifying operation based upon a hint 失效
标题翻译：基于提示执行部分缓存行存储修改操作
公开(公告)号：US08332588B2
公开(公告)日：2012-12-11
申请号：US13349315
申请日：2012-01-12
申请人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/04
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译：分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由存储修改结构随后由所述预处理代码引用。生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。

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