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91. 发明授权

US06306752B1 Connection component and method of making same 有权
标题翻译：连接组件及其制作方法
公开(公告)号：US06306752B1
公开(公告)日：2001-10-23
申请号：US09396048
申请日：1999-09-15
申请人： Thomas H. DiStefano , Joseph Fjeslstad , John W. Smith
发明人： Thomas H. DiStefano , Joseph Fjeslstad , John W. Smith
IPC分类号： H01L214763
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/3114 , H01L2224/50
摘要： A method of making a connection component for a microelectronic element includes providing a sheet comprising an electrically conductive layer, a photoresist layer overlying the conductive layer and a photoimageable dielectric layer disposed under the conductive layer. The method includes lithographically forming at least one opening in the photoresist layer to uncover a portion of the conductive layer, forming a plurality of circuit features from the conductive layer by removing the uncovered portion of the conductive layer, at least some of the circuit features being leads, and lithographically forming at least one aperture in the photoimageable dielectric layer.
摘要翻译：制造微电子元件的连接部件的方法包括提供包括导电层的片材，覆盖在导电层上的光致抗蚀剂层和设置在导电层下面的可光成像的电介质层。该方法包括在光致抗蚀剂层中光刻形成至少一个开口以露出导电层的一部分，通过去除导电层的未覆盖部分从导电层形成多个电路特征，至少一些电路特征为引线，并在光致成像介质层中光刻形成至少一个孔。

92. 发明授权

US06265765B1 Fan-out semiconductor chip assembly 失效
公开(公告)号：US06265765B1
公开(公告)日：2001-07-24
申请号：US08935962
申请日：1997-09-23
申请人： Thomas H. DiStefano , John W. Smith , Tony Faraci
发明人： Thomas H. DiStefano , John W. Smith , Tony Faraci
IPC分类号： H01L2302
CPC分类号： H01L21/4839 , H01L23/22 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/642 , H01L24/72 , H01L2224/16225 , H01L2224/45124 , H01L2224/73253 , H01L2224/81904 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/351 , H05K1/118 , H05K3/361 , H05K3/4084 , H05K2201/0133 , H05K2201/0394 , H05K2201/0397 , H05K2201/09081 , H05K2201/091 , H05K2203/063 , H01L2924/00 , H01L2224/48
摘要： A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

93. 发明授权

US06197665B1 Lamination machine and method to laminate a coverlay to a microelectronic package 有权
标题翻译：层压机和将覆盖层层压到微电子封装的方法
公开(公告)号：US06197665B1
公开(公告)日：2001-03-06
申请号：US09292640
申请日：1999-04-15
申请人： Thomas H. DiStefano , Craig S. Mitchell , Tan Nguyen
发明人： Thomas H. DiStefano , Craig S. Mitchell , Tan Nguyen
IPC分类号： H01L2136
CPC分类号： H01L21/67126 , H01L21/67092
摘要： A lamination machine includes means for using gas pressure to bring a coverlay and a microelectronic package into intimate contact and means for heating a coverlay adhesive in order to seal the coverlay to the package. A method of laminating a coverlay to a microelectronic package using the lamination machine includes using gas pressure to bring a coverlay into intimate contact with a microelectronic package. The method also includes heating an adhesive on the coverlay in order to adhere the coverlay to the package. Once the coverlay is laminated to the package, the package can be encapsulated with a curable encapsulant composition. The method may also include decreasing the pressure in the chamber disposed above the package to reduce voids and bubble and/or regulating the pressure in a bladder disposed in a chamber below the package. The lamination machine may also include a pressurized bladder which is used to support the microelectronic package and minimize stress on the leads during the lamination process.
摘要翻译：层压机包括用于使气体压力使盖板和微电子封装件紧密接触的装置，以及用于加热覆盖层粘合剂以便将覆盖物密封到包装的装置。使用层压机将覆盖层层压到微电子封装的方法包括使用气体压力使覆盖物与微电子封装紧密接触。该方法还包括加热覆盖物上的粘合剂以便将覆盖物粘附到包装上。一旦覆盖层被层压到包装上，封装可以用可固化的密封剂组合物包封。该方法还可以包括减小设置在包装上方的室中的压力，以减少空气和气泡和/或调节设置在包装下方的室中的气囊中的压力。层压机还可以包括用于支撑微电子封装并且在层压过程期间使引线上的应力最小化的加压囊。

94. 发明授权

US5994222A Method of making chip mountings and assemblies 失效
标题翻译：制造芯片安装和组件的方法
公开(公告)号：US5994222A
公开(公告)日：1999-11-30
申请号：US845786
申请日：1997-04-25
申请人： John W. Smith , Thomas H. DiStefano
发明人： John W. Smith , Thomas H. DiStefano
IPC分类号： H01L23/31 , H01L21/00
CPC分类号： H01L23/3107 , H01L24/97 , H01L2224/50 , H01L2224/97 , H01L2924/01082 , H01L2924/12042
摘要： A bonding component for electrically connecting a semiconductor chip or wafer to a support substrate includes a dielectric layer having a central region, elongated slots defining the central region, and a peripheral region surrounding the slots. Metallic bonding pads are arranged on the central region, and leads extend from the bonding pads to the edge of the central region and extending partially across the elongated slots. The leads are detached from the peripheral region of the dielectric layer on the side of the slots opposite the central region. The leads are adapted to be deformed during bonding to a semiconductor chip or wafer. To form the bonding component, a dielectric layer is first provided having a central region, slots and a peripheral region. A metallic structure is also provided having bonding pads on the central region, and leads electrically connected to the bonding pads and to a plating bus disposed in the peripheral region. A resist is applied to the metallic structure in zones separating the leads, the metallic structure is plated in regions outside the zones with an etch resistant metal, the resist is removed and the leads are etched so as to form gaps in the metallic structure over the elongated slots.
摘要翻译：用于将半导体芯片或晶片电连接到支撑衬底的接合部件包括具有中心区域的介电层，限定中心区域的细长槽和围绕槽的周边区域。金属接合焊盘布置在中心区域上，并且引线从焊盘延伸到中心区域的边缘并且部分延伸穿过细长槽。引线与介质层的与中心区域相对的一侧的外围区域分离。引线适于在与半导体芯片或晶片接合期间变形。为了形成接合部件，首先提供具有中心区域，槽和周边区域的电介质层。还提供了一种金属结构，在中心区域具有接合焊盘，并且引线电连接到接合焊盘和设置在周边区域中的电镀母线。在分离引线的区域中将金属结构施加抗蚀剂，金属结构用耐蚀刻金属镀在区域外的区域中，去除抗蚀剂并蚀刻引线以在金属结构上形成间隙细长的槽。

95. 发明授权

US5801441A Microelectronic mounting with multiple lead deformation and bonding 失效
公开(公告)号：US5801441A
公开(公告)日：1998-09-01
申请号：US440665
申请日：1995-05-15
申请人： Thomas H. DiStefano , John W. Smith
发明人： Thomas H. DiStefano , John W. Smith
IPC分类号： H01L21/60 , H01L21/30 , H01L21/48 , H01L21/603 , H01L23/12 , H01L23/22 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/64 , H01R12/71 , H05K1/11 , H05K3/36 , H05K3/40 , H01L23/52 , H01R4/58 , H01R9/09
CPC分类号： H01L23/4985 , H01L21/4839 , H01L23/22 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/642 , H01L24/72 , H05K3/4084 , H01L2224/16 , H01L2224/45124 , H01L2224/73253 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01066 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/07802 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025 , H01L2924/351 , H05K1/118 , H05K2201/0133 , H05K2201/0394 , H05K2201/0397 , H05K2201/09081 , H05K2201/091 , H05K2203/063 , H05K3/361 , Y10T29/49126 , Y10T29/49144 , Y10T29/49158
摘要： A microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

96. 发明授权

US5640761A Method of making multi-layer circuit 失效
标题翻译：制作多层电路的方法
公开(公告)号：US5640761A
公开(公告)日：1997-06-24
申请号：US478420
申请日：1995-06-07
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K3/36
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottom end of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上具有接触的电路板堆叠，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而制成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

97. 发明授权

US5583321A Multi-layer circuit construction methods and structures with customization features and components for use therein 失效
标题翻译：多层电路构造方法和结构，具有用于其中的定制特征和组件
公开(公告)号：US5583321A
公开(公告)日：1996-12-10
申请号：US443706
申请日：1995-05-15
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K1/02
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

98. 发明授权

US5570504A Multi-Layer circuit construction method and structure 失效
标题翻译：多层电路构造方法与结构
公开(公告)号：US5570504A
公开(公告)日：1996-11-05
申请号：US393165
申请日：1995-02-21
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K3/36
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

99. 发明授权

US5558928A Multi-layer circuit structures, methods of making same and components for use therein 失效
标题翻译：多层电路结构，制造方法及其中使用的组件
公开(公告)号：US5558928A
公开(公告)日：1996-09-24
申请号：US278426
申请日：1994-07-21
申请人： Thomas H. DiStefano , Scott G. Ehrenberg , Igor Y. Khandros
发明人： Thomas H. DiStefano , Scott G. Ehrenberg , Igor Y. Khandros
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K1/02 , H05K3/40 , H05K3/42 , H05K3/46 , B32B9/00
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49156 , Y10T29/49165 , Y10T428/239 , Y10T428/24917
摘要： A multi-layer circuit panel assembly is formed by laminating circuit panels with interposers incorporating flowable conductive material at interconnect locations and a flowable dielectric materials at locations other than the interconnect locations. Excess materials are captured in reservoirs such as within vias in the circuit panels and apertures in interior elements within the interposers. The flowable materials of the interposers, together with the reservoirs, allow the interposers to compress and take up tolerances in the components. The flowable dielectric material encapsulates conductors on the surfaces of the circuit panels.
摘要翻译：多层电路板组件通过层叠具有在互连位置处并入可流动导电材料的插入件的电路板和在互连位置之外的位置处的可流动电介质材料形成。过多的材料被捕获在储存器中，例如电路板中的通孔内和插入件内的内部元件中的孔。插入件的可流动材料与储存器一起允许内插件压缩并占据部件中的公差。可流动的电介质材料封装电路板表面上的导体。

100. 发明授权

US5536909A Semiconductor connection components and methods with releasable lead support 失效
标题翻译：半导体连接元件和方法具有可释放的引线支撑
公开(公告)号：US5536909A
公开(公告)日：1996-07-16
申请号：US320310
申请日：1994-10-13
申请人： Thomas H. DiStefano , Gary W. Grube , Igor Y. Khandros , Gaetan Mathiew
发明人： Thomas H. DiStefano , Gary W. Grube , Igor Y. Khandros , Gaetan Mathiew
IPC分类号： H01L21/60 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/50 , H05K1/18 , H05K3/36 , H05K3/40 , H05K1/02
CPC分类号： H01L23/49572 , H01L23/3107 , H01L23/49838 , H01L23/4985 , H01L23/49861 , H01L24/01 , H01L2924/01082 , H01L2924/12042 , H05K3/361 , H05K3/4084 , Y10T29/49121 , Y10T29/4913 , Y10T29/49135 , Y10T29/49218 , Y10T29/49222
摘要： A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.
摘要翻译：用于将半导体芯片电连接到支撑衬底的连接部件包含限定间隙的优选介电支撑结构。引线延伸穿过这些间隙，使得引线支撑在间隙的两侧。因此，引线可以通过将连接部件与芯片对准而大致对准芯片上的触点。每个引线被布置成使得当向引线施加向下的力时，一端可相对于支撑结构移位。这允许引线通过使每个引线与工具接合并将引线向下抵靠接触件而连接到芯片上的触点。优选地，每个引线包括与间隙的一侧相邻的易碎部分，并且当引线与触点接合时，易碎部分断裂。引线与芯片上的触点的最终对准由焊接工具提供，其具有适于控制引线位置的特征。

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