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91. 发明授权

US09613964B2 Semiconductor device including a memory cell 有权
公开(公告)号：US09613964B2
公开(公告)日：2017-04-04
申请号：US13034278
申请日：2011-02-24
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L27/108 , H01L27/105 , G11C11/24 , H01L27/1156 , H01L27/12 , H01L49/02
CPC分类号： H01L27/105 , G11C11/24 , H01L27/1052 , H01L27/108 , H01L27/10808 , H01L27/1156 , H01L27/1225 , H01L28/60
摘要： A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.

92. 发明授权

US08959401B2 System operations management apparatus, system operations management method and program storage medium 有权
标题翻译：系统运行管理装置，系统运行管理方法和程序存储介质
公开(公告)号：US08959401B2
公开(公告)日：2015-02-17
申请号：US13133718
申请日：2010-10-13
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06F11/00 , G06Q10/02 , G06F11/34
CPC分类号： G06F11/079 , G06F11/0709 , G06F11/0751 , G06F11/0787 , G06F11/3452 , G06Q10/02
摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.
摘要翻译：在系统运行管理装置中，降低了在检测未来的故障时提供判定准则时对系统管理员的负担。系统运行管理装置1包括演奏信息存储单元12，模型生成单元30和分析单元31.演奏信息存储单元12以时间序列存储包括系统中的多种类型的演奏值的演奏信息。模型生成单元30对于具有多个属性中的一个的多个周期中的每一个，生成包括存储在演奏信息存储单元12中的不同类型的演奏值之间的一个或多个相关性的相关模型。分析单元31通过使用输入的演奏信息和与已经获取了输入的演奏信息的时段的属性相对应的相关模型来执行已经输入的系统的演奏信息的异常检测。

93. 发明授权

US08809851B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08809851B2
公开(公告)日：2014-08-19
申请号：US13101644
申请日：2011-05-05
申请人： Shunpei Yamazaki , Kiyoshi Kato , Yutaka Shionoiri , Yusuke Sekine , Kazuma Furutani , Hiromichi Godo
发明人： Shunpei Yamazaki , Kiyoshi Kato , Yutaka Shionoiri , Yusuke Sekine , Kazuma Furutani , Hiromichi Godo
IPC分类号： H01L29/12
CPC分类号： H01L29/7869 , G11C16/0433 , G11C16/26 , H01L27/11521 , H01L27/1156 , H01L27/1225 , H01L28/40 , H01L29/41733 , H01L29/78621
摘要： A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.
摘要翻译：提供了包括在第一晶体管之上的第一晶体管和第二晶体管和电容器的半导体器件。第二晶体管的半导体层包括偏移区域。在设置有偏移区域的第二晶体管中，可以减小第二晶体管的截止电流。因此，可以提供能够长时间保持数据的半导体器件。

94. 发明授权

US08801300B2 Fiber optic cable end fixture and fiber optic cable end fixing method 有权
标题翻译：光缆端头固定和光缆端固定方法
公开(公告)号：US08801300B2
公开(公告)日：2014-08-12
申请号：US13697423
申请日：2011-05-12
申请人： Hajime Arao , Kiyoshi Kato
发明人： Hajime Arao , Kiyoshi Kato
IPC分类号： G02B6/36 , G02B6/00
CPC分类号： G02B6/3887 , G02B6/4477
摘要： A fiber optic cable fixture 1 has a joint member 3, a swaging member 4, and a fastening member 5. The joint member 3 has a cylindrical shape in which a through hole 10 is formed and includes a joint section 11 joined to another member, a male screw 12, and a cylindrical section 13 that is smaller in diameter than the male screw 12 and that is covered with a jacket 7 and tension fibers. The swaging member 4 is fitted to the cylindrical section 13 while covered with the jacket 7. A female screw 16 is formed at one end of an inner peripheral surface of the fastening member 5. A tapered surface 17 is formed on another end of the inner peripheral surface of the fastening member 5.
摘要翻译：光缆固定件1具有接头构件3，锻模构件4和紧固构件5.接合构件3具有圆筒形状，其中形成有通孔10，并且包括接合到另一构件的接合部11，外螺纹12和直径小于外螺纹12并被护套7和张力纤维覆盖的圆筒部13。模锻构件4在被套筒7覆盖的同时被装配到圆筒形部分13上。内螺纹16形成在紧固构件5的内周面的一端。锥形表面17形成在内侧的另一端紧固件5的外周表面。

95. 发明授权

US08716814B2 Wireless processor, wireless memory, information system, and semiconductor device 有权
标题翻译：无线处理器，无线存储器，信息系统和半导体器件
公开(公告)号：US08716814B2
公开(公告)日：2014-05-06
申请号：US11571859
申请日：2005-07-07
申请人： Shunpei Yamazaki , Kiyoshi Kato , Jun Koyama , Yutaka Shionoiri
发明人： Shunpei Yamazaki , Kiyoshi Kato , Jun Koyama , Yutaka Shionoiri
IPC分类号： H01L27/14
CPC分类号： H01L27/1222 , G06K19/0723 , H01L23/5387 , H01L23/66 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/1255 , H01L27/13 , H01L29/78621 , H01L29/78648 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
摘要翻译：本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，半导体膜分隔成10至200nm的厚度的岛状物以及天线。晶体管固定在柔性基板上。其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

96. 发明授权

US08680520B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08680520B2
公开(公告)日：2014-03-25
申请号：US12949631
申请日：2010-11-18
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L29/12
CPC分类号： H01L27/1203 , G11C11/403 , G11C11/405 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/1156 , H01L27/1225
摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer.
摘要翻译：本发明的目的是提供一种具有新颖结构的半导体器件。半导体器件包括第一布线，第二布线，第三布线，第四布线，包括第一栅电极，第一源电极和第一漏电极的第一晶体管，以及包括第二栅电极的第二晶体管，第二源电极和第二漏电极。第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。

97. 发明授权

US08619470B2 Semiconductor memory device with long data holding period 有权
标题翻译：具有长数据保持期的半导体存储器件
公开(公告)号：US08619470B2
公开(公告)日：2013-12-31
申请号：US13161616
申请日：2011-06-16
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/04
CPC分类号： G11C11/403 , G11C16/0433
摘要： A semiconductor device includes a source line, a bit line, and first to m-th (m is a natural number) memory cells connected in series between the source line and the bit line. Each of the first to m-th memory cells includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, and a capacitor. The node of the k-th memory cell is supplied with a potential higher than that of the second gate terminal of the k-th memory cell in a data holding period in which the second gate terminal is supplied with a potential at which the second transistor is turned off.
摘要翻译：半导体器件包括源极线，位线以及串联连接在源极线和位线之间的第一至第m（m为自然数）的存储单元。第一至第m存储单元中的每一个包括具有第一栅极端子，第一源极端子和第一漏极端子的第一晶体管，具有第二栅极端子的第二晶体管，第二源极端子和第二漏极端子，和电容器。第k个存储单元的节点在其第二栅极端子被提供有电位的数据保持周期中被提供有高于第k个存储单元的第二栅极端子的电位，在该电位下第二晶体管已关闭

98. 发明授权

US08610187B2 Semiconductor device 有权
公开(公告)号：US08610187B2
公开(公告)日：2013-12-17
申请号：US12966611
申请日：2010-12-13
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L27/105 , H01L27/108
CPC分类号： H01L27/115 , G11C16/0416 , H01L21/28518 , H01L23/528 , H01L27/10805 , H01L27/10855 , H01L27/11517 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L28/40 , H01L29/24 , H01L29/6659 , H01L29/78 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

99. 发明授权

US08598648B2 Semiconductor device and driving method of semiconductor device 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US08598648B2
公开(公告)日：2013-12-03
申请号：US13044674
申请日：2011-03-10
申请人： Kiyoshi Kato , Satohiro Okamoto , Shuhei Nagatsuka
发明人： Kiyoshi Kato , Satohiro Okamoto , Shuhei Nagatsuka
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , H01L27/115 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/13 , H01L28/60
摘要： A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.
摘要翻译：使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以长时间保存数据。各半导体装置的存储单元中的包含氧化物半导体的晶体管串联连接，因此，包括存储单元中的氧化物半导体的晶体管的源极和在相邻的存储单元中包括氧化物半导体的晶体管的漏电极可以彼此连接。因此，可以减少存储单元占用的面积。

100. 发明授权

US08576636B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08576636B2
公开(公告)日：2013-11-05
申请号：US13175090
申请日：2011-07-01
申请人： Kiyoshi Kato , Takanori Matsuzaki , Hiroki Inoue , Shuhei Nagatsuka
发明人： Kiyoshi Kato , Takanori Matsuzaki , Hiroki Inoue , Shuhei Nagatsuka
IPC分类号： G11C11/34
CPC分类号： H01L27/1156 , G11C11/404 , G11C16/0441 , H01L27/1207
摘要： A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.
摘要翻译：包括在存储单元阵列中的多个存储单元被分成多个块，每个多行。公共位线通过块中的选择晶体管电连接到分割位线。一个存储单元包括第一晶体管，第二晶体管和电容器。第一晶体管包括第一沟道形成区。第二晶体管包括第二沟道形成区域。第一沟道形成区域包括与第二沟道形成区域的半导体材料不同的半导体材料。

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