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91. 发明授权

US07998810B2 Methods of forming integrated circuit devices having stacked gate electrodes 有权
标题翻译：形成具有层叠栅电极的集成电路器件的方法
公开(公告)号：US07998810B2
公开(公告)日：2011-08-16
申请号：US12424922
申请日：2009-04-16
申请人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66545
摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
摘要翻译：提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

92. 发明授权

US07968410B2 Method of fabricating a semiconductor device using a full silicidation process 有权
标题翻译：使用全硅化工艺制造半导体器件的方法
公开(公告)号：US07968410B2
公开(公告)日：2011-06-28
申请号：US12460945
申请日：2009-07-27
申请人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
发明人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28123 , H01L21/28282
摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
摘要翻译：一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

93. 发明授权

US07521357B2 Methods of forming metal wiring in semiconductor devices using etch stop layers 有权
标题翻译：使用蚀刻停止层在半导体器件中形成金属布线的方法
公开(公告)号：US07521357B2
公开(公告)日：2009-04-21
申请号：US11063936
申请日：2005-02-23
申请人： Sang-woo Lee , Gil-heyun Choi , Sang-bom Kang , Jong-myeong Lee , Jin-ho Park
发明人： Sang-woo Lee , Gil-heyun Choi , Sang-bom Kang , Jong-myeong Lee , Jin-ho Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76841 , H01L21/76856 , H01L21/76877
摘要： A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer inside the contact hole. A conductive layer can be formed on the etch stop layer outside the contact hole and on an exposed conductive pattern inside the contact hole and on a sidewall of the contact hole and a metal layer can be formed on the conductive layer to fill the contact hole.
摘要翻译：在半导体器件中形成金属布线的方法可以包括在形成在绝缘层中的接触孔之外形成蚀刻停止层，并避免在接触孔内形成蚀刻停止层。可以在接触孔外部的蚀刻停止层上形成导电层，并且在接触孔内部和接触孔的侧壁上的暴露的导电图案上形成导电层，并且可以在导电层上形成金属层以填充接触孔。

94. 发明授权

US07223689B2 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 有权
标题翻译：在形成阻挡金属层的同时形成欧姆层的半导体器件中形成金属接触的方法
公开(公告)号：US07223689B2
公开(公告)日：2007-05-29
申请号：US11112356
申请日：2005-04-22
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
摘要翻译：通过在硅衬底上形成具有接触孔的绝缘层，形成半导体器件中的金属接触。钴层形成在接触孔的底壁和内壁上。在钴层上形成钛层的同时，在接触孔的底部形成钴硅化物层。在钛层上形成插塞以填充接触孔。

95. 发明授权

US06849555B2 Wafer processing apparatus and wafer processing method using the same 有权
标题翻译：晶圆加工装置及使用其的晶片加工方法
公开(公告)号：US06849555B2
公开(公告)日：2005-02-01
申请号：US10449522
申请日：2003-05-30
申请人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
发明人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
IPC分类号： C23C14/56 , C23C16/44 , H01L21/00 , H01L21/02 , H01L21/285 , H01L21/302 , H01L21/461 , H01L21/677 , H01L21/768
CPC分类号： H01L21/67167 , H01L21/2855 , H01L21/28556 , H01L21/67017 , H01L21/67201 , H01L21/67739 , H01L21/76882 , H01L21/76888 , Y10S438/974
摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.
摘要翻译：提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。晶片上的预定层在负载锁定室或氧气氛室中被氧化。

96. 发明授权

US5982039A Completely buried contact holes 失效
标题翻译：完全埋入接触孔
公开(公告)号：US5982039A
公开(公告)日：1999-11-09
申请号：US48391
申请日：1998-03-26
申请人： Woo-sang Jung , Gil-heyun Choi , Ji-soon Park , Byeong-jun Kim
发明人： Woo-sang Jung , Gil-heyun Choi , Ji-soon Park , Byeong-jun Kim
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L23/485 , H01L23/53223 , H01L2924/0002
摘要： A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole. The method includes forming in an insulator adjacent a contact hole a region of material of a higher thermal conductivity than the insulating layer, depositing a metal in the contact hole and heating the metal, the insulating layer and the region of material of a higher thermal conductivity to flow the metal into the contact hole so as to completely bury the contact hole.
摘要翻译：公开了一种用于形成完全埋入的接触孔的方法和在互连结构中具有完全埋入的接触孔的半导体器件。完全埋入的接触孔包括具有形成在其中的接触孔的第一导热性的第一绝缘层。形成在与接触孔的位置相邻的第一绝缘层中的第二导热材料的区域。第二热导率大于第一热导率，使得材料区域的热导率大于绝缘层的热导率。在孔中形成金属，完全埋入接触孔。该方法包括在绝缘体中邻近形成绝缘层的导热系数较高的材料区域，在接触孔中沉积金属并加热金属，绝缘层和导热系数较高的材料区域将金属流入接触孔，以完全埋入接触孔。

97. 发明授权

US5544771A Method for manufacturing a collimator 失效
标题翻译：准直仪的制造方法
公开(公告)号：US5544771A
公开(公告)日：1996-08-13
申请号：US493735
申请日：1995-06-22
申请人： Jueng-gil Lee , Sun-hoo Park , Gil-heyun Choi
发明人： Jueng-gil Lee , Sun-hoo Park , Gil-heyun Choi
IPC分类号： C23C14/34 , B21D47/04 , G21K1/02 , H01J37/34 , H01L21/203 , H01L21/265 , H01L21/285 , H01L21/74 , C23F1/00 , B04C1/22
CPC分类号： G21K1/025 , H01J37/34 , H01J37/3447
摘要： A method for manufacturing a collimator comprising the steps of patterning a plurality of thin metal strips into a plurality of basic plates, and forming grooves or ridges on front and back surfaces of each basic plates. Thereafter, the thin strips are folded, mated, and welded together to form pillar cells within the collimator.
摘要翻译：一种用于制造准直器的方法，包括以下步骤：将多个薄金属条图案化成多个基板，以及在每个基板的前表面和后表面上形成凹槽或脊。此后，薄带被折叠，交配并焊接在一起以在准直器内形成柱状电池。

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