会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 91. 发明授权
    • Data sampling method and apparatus using through-transition counts to reject worst sampling position
    • 数据采样方法和使用过渡计数的装置来排除最差采样位置
    • US07991096B1
    • 2011-08-02
    • US10842231
    • 2004-05-10
    • Bruce KimHoon ChoiGyudong Kim
    • Bruce KimHoon ChoiGyudong Kim
    • H04L7/00
    • H04L7/033H04J3/0608
    • A data sampling circuit that employs an oversampling clock to oversample a data signal, a phase tracking circuit for use in such a sampling circuit, and a receiver and system including such a sampling circuit. Preferably, phase tracking is implemented by systematically identifying and rejecting at least one worst sampling position, and sampling the data signal at a non-rejected sampling position. Preferably, phase tracking is accomplished by counting through-transitions of edges of the sampled data signal through each oversampling position, and rejecting an oversampling position having a highest count of through-transitions. In some embodiments, different phase tracking methods (at least one of which includes the step of generating through-transition counts) are used for different types of input data. Other aspects of the invention are methods for determining an oversampling position for oversampling a data signal, and methods for oversampling a data signal including by generating through-transition counts.
    • 使用过采样时钟对数据信号进行过采样的数据采样电路,用于这种采样电路的相位跟踪电路以及包括这种采样电路的接收机和系统。 优选地,相位跟踪通过系统地识别和拒绝至少一个最差采样位置并且在未拒绝的采样位置对数据信号进行采样来实现。 优选地,通过对采样数据信号的边缘通过每个过采样位置的过渡进行计数,以及拒绝具有最高通过过渡计数的过采样位置来实现相位跟踪。 在一些实施例中,不同类型的输入数据使用不同的相位跟踪方法(其中至少一个包括生成通过转换计数的步骤)。 本发明的其它方面是用于确定用于过采样数据信号的过采样位置的方法,以及用于过采样数据信号的方法,包括通过产生通过转换计数。
    • 94. 发明申请
    • TRANSMISSION AND HANDLING OF THREE-DIMENSIONAL VIDEO CONTENT
    • 三维视频内容的传输和处理
    • US20110149032A1
    • 2011-06-23
    • US12966194
    • 2010-12-13
    • Hoon ChoiDaekyeung KimWooseung YangYoung Il KimJeoong Sung Park
    • Hoon ChoiDaekyeung KimWooseung YangYoung Il KimJeoong Sung Park
    • H04N13/00
    • H04N19/597H04N13/167H04N13/194
    • Embodiments of the invention are generally directed to transmission and handling of three-dimensional video content. An embodiment of a method includes receiving a multimedia data stream including video data utilizing an interface protocol and determining that the received video data includes three-dimensional (3D) video data, where each frame of the video data includes a first vertical synchronization (Vsync) signal prior to an active data region, the active data region including a first data region and a second data region. The method further includes converting the 3D video data from a 3D data format to a two-dimensional (2D) video format, where converting the 3D video data includes identifying a region between the first data region and the second data region, inserting a second Vsync signal between the first data region and the second data region, and providing an identifier to distinguish between the first data region and the second data region.
    • 本发明的实施例一般涉及三维视频内容的传输和处理。 一种方法的实施例包括使用接口协议接收包括视频数据的多媒体数据流,并确定所接收的视频数据包括三维(3D)视频数据,其中每个视频数据帧包括第一垂直同步(Vsync) 信号在活动数据区之前,活动数据区包括第一数据区和第二数据区。 该方法还包括将3D视频数据从3D数据格式转换成二维(2D)视频格式,其中转换3D视频数据包括识别第一数据区域和第二数据区域之间的区域,插入第二Vsync 信号在第一数据区域和第二数据区域之间,并且提供标识符以区分第一数据区域和第二数据区域。
    • 95. 发明授权
    • Control bus for connection of electronic devices
    • 用于连接电子设备的控制总线
    • US07856520B2
    • 2010-12-21
    • US11969852
    • 2008-01-04
    • Shrikant RanadeAlexander PeysakhovichHyuck Jae LeeHoon Choi
    • Shrikant RanadeAlexander PeysakhovichHyuck Jae LeeHoon Choi
    • G06F13/42G06F13/00G06F13/368
    • G09G5/006G09G2370/10G09G2370/12H04L69/08
    • A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus.
    • 一种用于连接电子设备的控制总线的方法和装置。 一种方法的实施例包括将发送设备耦合到接收设备,包括在发送设备和接收设备之间连接控制总线,控制总线是双向的单行总线。 该方法还包括获取控制总线对发射设备或接收设备的控制,其中设备获得控制变为启动器,而另一设备成为跟随器。 一个或多个控制信号被转换成一个或多个数据分组,其中一个或多个控制信号中的每一个表示多种不同类型的控制信号之一。 生成的数据分组通过控制总线从发起者发送到跟随者。
    • 96. 发明授权
    • Parameter scanning for signal over-sampling
    • 信号过采样参数扫描
    • US07782934B2
    • 2010-08-24
    • US11856640
    • 2007-09-17
    • Hoon Choi
    • Hoon Choi
    • H03H7/30
    • H04L25/03038H04L25/03019H04L25/03885
    • A method and apparatus for parameter scanning for signal over-sampling. An embodiment of an apparatus includes an equalizer to equalize received data values, and a sampler to over-sample the equalized data. The apparatus includes an eye monitor to generate information regarding quality of signal eyes for the over-sampled data, and an equalization monitor to generate information regarding sufficiency of signal equalization. The apparatus further includes a scan engine to scan possible values of a plurality of parameters for the apparatus.
    • 用于信号过采样的参数扫描的方法和装置。 装置的实施例包括均衡器以均衡接收的数据值,以及采样器以对均衡数据进行过采样。 该装置包括眼睛监视器,用于产生关于过采样数据的信号眼的质量的信息,以及用于产生关于信号均衡充分性的信息的均衡监视器。 该装置还包括扫描引擎,用于扫描装置的多个参数的可能值。
    • 97. 发明授权
    • Heat reflector and substrate processing apparatus comprising the same
    • 热反射器和包括其的基板处理装置
    • US07772527B2
    • 2010-08-10
    • US11405563
    • 2006-04-18
    • Hoon Choi
    • Hoon Choi
    • F27B5/06F27B5/14F27D19/00F21V7/00F21V7/10F21V7/16
    • H01L21/67115F27B5/04F27B17/0025Y10T428/24273
    • A substrate processing apparatus includes a process chamber including upper and lower quartz walls, a substrate support disposed in the process chamber, radiant heaters respectively provided above and below the quartz walls of the chamber, and heat reflectors disposed outside the process chamber for reflecting heat towards the substrate support. Each of the heat reflectors has heating has a first thermally reflective section oriented to reflect the heat towards an outer peripheral region of the substrate support and a second thermally reflective section oriented to reflect the heat towards a central region of the substrate support. Each heat reflector also has a reflection angle adjusting mechanism by which an angle at which the second thermally reflective section reflects heat can be adjusted. The angle is adjusted depending on the temperature distribution across the substrate so that the substrate can be processed uniformly.
    • 基板处理装置包括具有上,下石英壁的处理室,设置在处理室中的基板支撑件,分别设置在室的石英壁上方和下方的辐射加热器,以及设置在处理室外部的热反射器,用于将热量反射 衬底支撑。 每个热反射器具有加热,其具有第一热反射部分,其被定向成朝着基板支撑件的外周区域反射热量;以及第二热反射部件,其被定向成朝着基板支撑件的中心区域反射热量。 每个热反射器还具有反射角调节机构,通过该反射角调节机构可以调节第二热反射部分反射热量的角度。 根据衬底上的温度分布来调节角度,使得可以均匀地处理衬底。
    • 98. 发明授权
    • Delay locked loop circuit
    • 延时锁定回路电路
    • US07750699B2
    • 2010-07-06
    • US12010964
    • 2008-01-31
    • Hoon Choi
    • Hoon Choi
    • H03L7/06
    • H03L7/0814G11C7/1072G11C7/222H03L7/0805
    • A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.
    • DLL电路和同步存储器件在功率下降模式下执行稳定的操作,尽管进入/退出掉电模式是快速重复的。 同步存储器件在正常模式和掉电模式下工作。 延迟锁定环(DLL)在退出掉电模式时产生具有冻结锁定信息的DLL时钟。 当在进入掉电模式之后的预定时间过去时,控制器阻止DLL的相位更新操作,从而获得在正常模式下进行的相位更新操作的时间余量。
    • 99. 发明授权
    • Delay locked loop circuit
    • 延时锁定回路电路
    • US07605622B2
    • 2009-10-20
    • US11478094
    • 2006-06-30
    • Hoon ChoiJae-Jin Lee
    • Hoon ChoiJae-Jin Lee
    • H03L7/06
    • H03L7/0814G06F7/68H03L7/0805
    • A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
    • 具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。 断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。 源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。 相位更新单元基于DLL源时钟信号执行相位更新操作,以输出DLL时钟信号。