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91. 发明授权

US07054985B2 Multiple hardware partitions under one input/output hub 失效
标题翻译：一个输入/输出集线器下的多个硬件分区
公开(公告)号：US07054985B2
公开(公告)日：2006-05-30
申请号：US10200247
申请日：2002-07-23
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： G06F13/28 , G06F13/26 , G06F13/36
CPC分类号： G06F12/084 , G06F12/0875 , G06F13/4027
摘要： A method and a mechanism are capable of partitioning computer hardware components or elements at the level of individual processing paths, or ropes. Incoming and outgoing queues may be designed such that transactions to/from one rope do not interfere with another rope. Each common queue is treated as a collection of virtual queues/buffers. Transaction generated by computer system components may include both the address and the partition identification (ID) of the component. This ensures that components of one partition cannot adversely affect components of another partition, or the entire computer system. The computer components include input/output (I/O) devices, such as ethernet cards, or other I/O devices. The method and mechanism may be adapted for use by computer components other than I/O devices.
摘要翻译：一种方法和机制能够在各个处理路径或绳索的级别上划分计算机硬件组件或元件。进出队列可以被设计成使得/来自一根绳索的交易不会干扰另一根绳索。每个公共队列被视为虚拟队列/缓冲区的集合。计算机系统组件生成的事务可以包括组件的地址和分区标识（ID）。这确保一个分区的组件不会对另一个分区或整个计算机系统的组件产生不利影响。计算机组件包括输入/输出（I / O）设备，如以太网卡或其他I / O设备。该方法和机构可以适用于除I / O设备之外的计算机组件使用。

92. 发明授权

US06910169B2 ECC code mechanism to detect wire stuck-at faults 有权
标题翻译： ECC代码机制，用于检测电线卡住故障
公开(公告)号：US06910169B2
公开(公告)日：2005-06-21
申请号：US10245260
申请日：2002-09-17
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： G01R31/02 , G06F11/10 , G06F13/00 , G11B20/18 , H03M13/15 , H04B17/00 , H03M13/00 , G01R31/28
CPC分类号： G11B20/1816 , G11B20/18
摘要： The inventive mechanism detects wire stuck-at faults, which can be used with any other ECC code. The inventive mechanism determines the number of 1's (or 0's) in the data portion and the ECC code of the data portion. This counted number is then provided with ECC code. The data portion, its ECC, the counted number, and its ECC are transmitted to the destination. At the destination, the message is decoded, and the number of 1's in the received message is compared with the counted number, if there is a discrepancy, then a wire fault is signaled. The mechanism may also detect any number of faults provided the number of 0 to 1 transitions is not the same as the number of 1 to 0 transitions. The mechanism can be reconfigured to work with any transmission wire width.
摘要翻译：本发明的机构检测线卡住故障，可以与任何其他ECC代码一起使用。本发明的机构确定数据部分中的1（或0）的数目和数据部分的ECC码。然后将该计数的数字提供ECC码。将数据部分，其ECC，计数和其ECC发送到目的地。在目的地，消息被解码，并且将接收到的消息中的1的数目与计数进行比较，如果存在差异，则发出有线故障。如果0到1个转换的数量与1到0个转换的数量不同，则该机制还可以检测任何数量的故障。该机构可以重新配置为与任何传输线宽度一起工作。

93. 发明授权

US06412046B1 Verification of cache prefetch mechanism 失效
标题翻译：缓存预取机制的验证
公开(公告)号：US06412046B1
公开(公告)日：2002-06-25
申请号：US09562130
申请日：2000-05-01
申请人： Debendra Das Sharma , Kevin Hauck , Daniel F. Li
发明人： Debendra Das Sharma , Kevin Hauck , Daniel F. Li
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： A method and apparatus automatically and easily verifies a cache line prefetch mechanism. The verification method includes a strict definition of which cache lines should be prefetched and which cache lines should not. The method also emphasizes unusual operating conditions. For example, by exercising boundary conditions, the method by stresses situations in which a microprocessor or chip is likely to produce errors. The method can verify prefetch without having to access or view any internal signals or buses inside the chip. The method can be adopted in any system-level verification methodology in simulation, emulation, or actual hardware. The method can be used in a system-level test set up along with a chip-level test set up without requiring knowledge of the internal state of the chip. In this case, checking is done at the chip boundary. The method is automated and performs strict checks on overprefetch, underprefetch, and the relative order in which fetch and prefetches must occur.
摘要翻译：一种方法和设备自动且容易地验证高速缓存行预取机制。验证方法包括严格定义哪些缓存行应该被预取，哪些缓存行不应该。该方法还强调不寻常的操作条件。例如，通过行使边界条件，微处理器或芯片可能产生错误的应力情况的方法。该方法可以验证预取，而无需访问或查看芯片内的任何内部信号或总线。该方法可以在仿真，仿真或实际硬件中的任何系统级验证方法中采用。该方法可用于系统级测试以及芯片级测试设置，而无需了解芯片的内部状态。在这种情况下，在码片边界进行检查。该方法是自动化的，并且对过度提取，低反应以及必须进行获取和预取的相对顺序执行严格的检查。

94. 发明授权

US5944843A Method and apparatus for using the unused bits of a data packet to transmit additional information 失效
标题翻译：用于使用数据分组的未使用位来发送附加信息的方法和装置
公开(公告)号：US5944843A
公开(公告)日：1999-08-31
申请号：US918696
申请日：1997-08-21
申请人： Debendra Das Sharma , John A. Wickeraad
发明人： Debendra Das Sharma , John A. Wickeraad
IPC分类号： H04L29/00 , H04L1/00 , H04L1/16 , H04L12/56 , H04L29/06 , H04L29/08 , G06F11/00
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0083 , H04L1/1671 , H04L47/35 , H04L1/16 , H04L2001/0095 , H04L69/22 , H04L69/324
摘要： A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet. The same predefined bit pattern is used for the unused bit positions when the integrity of the primary code word is verified at the destination. If it is desired to protect the secondary code word, a secondary ECC must also be stored in the data packet. In a second embodiment, the ECC is recalculated when a secondary code word is piggy-backed into the unused bit positions of the data packet. In this embodiment, the ECC associated with the data packet protects all data in the packet, including the primary and secondary code words.
摘要翻译：根据本发明的方法和装置使用数据分组的未使用的比特通过捎带“次”码字来发送附加信息到包含“主”码字的数据分组中。当主代码字和已经存储在数据分组中的任何辅助代码字在数据分组中留下足够的未使用空间以存储额外的辅助代码字时，副代码字可以被捎带到包含主代码字的数据分组中，并且当分组被路由到由主代码寻址的网络节点时由数据分组传播的路由通过（或在其结束于）由第二代码字寻址的网络节点，或者通过（或最终）网络节点可以将次要码字中继到由二次码字寻址的网络节点。在第一实施例中，为数据分组中的任何未使用位位置使用预定义位模式（例如全0）为主代码字生成ECC。当在目的地验证主码字的完整性时，相同的预定位位模式用于未使用的位位置。如果希望保护辅助码字，则辅助ECC也必须存储在数据包中。在第二实施例中，当第二码字被捎带到数据包的未使用位位置时，重新计算ECC。在该实施例中，与数据分组相关联的ECC保护分组中的所有数据，包括主要和次要代码字。

95. 发明申请

US20220262756A1 CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS 有权
公开(公告)号：US20220262756A1
公开(公告)日：2022-08-18
申请号：US17733545
申请日：2022-04-29
申请人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu , Swadesh Choudhary
发明人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu , Swadesh Choudhary
IPC分类号： H01L23/00 , H01L25/10 , G06F1/04 , H01L23/12 , H01L23/538
摘要： Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

96. 发明申请

US20220237138A1 LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT 有权
公开(公告)号：US20220237138A1
公开(公告)日：2022-07-28
申请号：US17708386
申请日：2022-03-30
申请人： Narasimha Lanka , Lakshmipriya Seshan , Swadesh Choudhary , Debendra Das Sharma , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Lakshmipriya Seshan , Swadesh Choudhary , Debendra Das Sharma , Zuoguo Wu , Gerald Pasdast
IPC分类号： G06F13/40 , G06F1/10
摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

97. 发明申请

US20200327088A1 STREAMING FABRIC INTERFACE 审中-公开
公开(公告)号：US20200327088A1
公开(公告)日：2020-10-15
申请号：US16914339
申请日：2020-06-27
申请人： Swadesh Choudhary , Debendra Das Sharma , Lee Albion
发明人： Swadesh Choudhary , Debendra Das Sharma , Lee Albion
IPC分类号： G06F13/42 , G06F1/10
摘要： An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

98. 发明授权

US10671476B2 In-band margin probing on an operational interconnect 审中-公开
公开(公告)号：US10671476B2
公开(公告)日：2020-06-02
申请号：US15761405
申请日：2015-09-26
申请人： Intel Corporation , Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
发明人： Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
IPC分类号： G06F11/08 , G06F13/14 , G06F11/10 , G06F11/22 , H04L1/00
摘要： There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

99. 发明申请

US20190324523A1 ALTERNATE PHYSICAL LAYER POWER MODE 审中-公开
公开(公告)号：US20190324523A1
公开(公告)日：2019-10-24
申请号：US16457930
申请日：2019-06-29
申请人： Michelle C. Jen , David J. Harriman , Zuoguo Wu , Debendra Das Sharma , Noam Dolev Geldbard
发明人： Michelle C. Jen , David J. Harriman , Zuoguo Wu , Debendra Das Sharma , Noam Dolev Geldbard
IPC分类号： G06F1/3234 , G06F1/3225 , G06F3/06
摘要： A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

100. 发明申请

US20190042380A1 CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING 审中-公开
公开(公告)号：US20190042380A1
公开(公告)日：2019-02-07
申请号：US15990372
申请日：2018-05-25
申请人： Debendra Das Sharma , Daniel S. Froelich
发明人： Debendra Das Sharma , Daniel S. Froelich
IPC分类号： G06F11/22 , G06F13/42
摘要： A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

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