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91. 发明申请

US20100077149A1 Method and Apparatus for Managing Cache Reliability 有权
标题翻译：用于管理缓存可靠性的方法和装置
公开(公告)号：US20100077149A1
公开(公告)日：2010-03-25
申请号：US12234619
申请日：2008-09-20
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F11/1064 , G06F2212/1032 , G06F2212/601
摘要： A method of configuring a cache includes identifying a plurality of cache configurations of a configurable cache for a processor-executable application unit. Each configuration has an associated error rate. A selected configuration is selected based at least in part on the associated error rate. The configurable cache is configured in accordance with the selected configuration for execution of the application-unit.
摘要翻译：配置高速缓存的方法包括识别用于处理器可执行应用单元的可配置高速缓存的多个高速缓存配置。每个配置都有相关的错误率。至少部分地基于相关联的错误率来选择所选择的配置。根据用于执行应用单元的所选配置来配置可配置高速缓存。

92. 发明申请

US20100064205A1 SELECTIVE CACHE WAY MIRRORING 有权
标题翻译：选择性高速缓存镜像
公开(公告)号：US20100064205A1
公开(公告)日：2010-03-11
申请号：US12204989
申请日：2008-09-05
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/00 , G06F12/02 , G06F7/02 , G06F12/08
CPC分类号： G06F12/0864 , G06F11/1064 , G06F12/126
摘要： A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation.
摘要翻译：数据处理系统具有多个方式的高速缓存电路。镜像控制逻辑指示多个方式的镜像方式对和非镜像方式。镜像方式对具有第一和第二种方式，其中第二种方式被配置为存储冗余的高速缓存数据字段以缓存第一种方式的数据字段。在一种形式中，响应于以第一种方式触发的地址或镜像方式对内的第二种方式的比较逻辑，从由地址的索引部分寻址的第一种方式的高速缓存数据与来自由地址的索引部分寻址的第二种方式来提供位奇偶校验错误信号。在另一种形式中，分配逻辑使用地址和行锁定信息的一部分来确定是否选择镜像或非镜像方式进行分配。

93. 发明申请

US20100057997A1 CACHE SNOOP LIMITING WITHIN A MULTIPLE MASTER DATA PROCESSING SYSTEM 有权
标题翻译：在多个主数据处理系统中进行CACHE SNOOP限制
公开(公告)号：US20100057997A1
公开(公告)日：2010-03-04
申请号：US12201216
申请日：2008-08-29
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1016
摘要： In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if the first processing circuitry is prevented from accessing the cache for more than a threshold amount of time. A signal is generated to indicate when the first processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.
摘要翻译：在数据处理系统中，仲裁响应于来自第一处理电路的访问请求对高速缓存的访问和由第二处理电路执行的事务而产生的窥探请求。监视高速缓存的访问以确定第一处理电路是否被阻止超过阈值的时间量访问高速缓存。生成信号以指示第一处理电路何时被阻止访问高速缓存超过阈值时间量。

94. 发明申请

US20090322411A1 CIRCUIT AND METHOD FOR AVOIDING SOFT ERRORS IN STORAGE DEVICES 有权
标题翻译：避免存储设备软错误的电路和方法
公开(公告)号：US20090322411A1
公开(公告)日：2009-12-31
申请号：US12164760
申请日：2008-06-30
申请人： William C. Moyer , Troy L. Cooper
发明人： William C. Moyer , Troy L. Cooper
IPC分类号： G06F11/16 , G06F17/50
CPC分类号： G06F17/505 , G06F11/00 , G06F17/5072 , G06F2217/14 , G11C5/005 , G11C29/70
摘要： A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement.
摘要翻译：识别电路设计中的存储元件。存储元件被替换为第一存储单元和第二存储单元。第二存储单元作为冗余存储单元操作到第一存储单元。第一存储单元的输出连接到比较器的第一输入端，第二存储单元的输出端连接到比较器的第二输入端。比较器提供错误指示器。确定第一存储单元，第二存储单元，比较器和一个或多个中间单元的放置。一个或多个中间单元被放置在第一存储单元和第二存储单元之间。使用比较器，第一存储单元，第二存储单元，一个或多个中间单元以及所确定的布局来创建集成电路。

95. 发明申请

US20090300294A1 UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS 有权
标题翻译：存储分配缓存错误恢复存储缓冲区的使用
公开(公告)号：US20090300294A1
公开(公告)日：2009-12-03
申请号：US12130570
申请日：2008-05-30
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3863
摘要： A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.
摘要翻译：处理器和高速缓存通过系统互连耦合到系统存储器。耦合到高速缓存的第一缓冲电路接收一个或多个数据字，并将一个或多个数据字存储在一个或多个条目的每一个中。响应于无错误的接收，将第一条目的一个或多个数据字写入高速缓存。耦合到高速缓存的第二缓冲电路具有用于存储存储请求的一个或多个条目。每个条目具有相关联的控制位，其确定从第一存储请求形成的条目是否是从第二缓冲电路写入系统存储器的有效条目。基于一个或多个数据字的无错误接收，相关联的控制位被设置为使得基于错误确定使第二缓冲电路中的条目无效的值。

96. 发明授权

US07627795B2 Pipelined data processor with deterministic signature generation 有权
标题翻译：具有确定性签名生成的流水线数据处理器
公开(公告)号：US07627795B2
公开(公告)日：2009-12-01
申请号：US11460086
申请日：2006-07-26
申请人： William C. Moyer , Jimmy Gumulja
发明人： William C. Moyer , Jimmy Gumulja
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00
CPC分类号： G01R31/318566 , G01R31/318547 , G11C29/1201
摘要： A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.
摘要翻译：流水线数据处理系统包括具有位于功能电路内的预定电路节点处的多个测试点的功能电路，与数据处理系统的流水线级相关联的至少一个分段存储元件，其被耦合以直接从多个测试点和多输入移位寄存器（MISR），其被耦合以从所述至少一个分段存储元件接收测试数据并提供MISR结果。在一个方面，所述至少一个登台存储元件具有多个分段存储元件，其中所述多个分段存储元件中的每一个对应于所述数据处理系统的不同流水线级。在另一方面，MISR结果与变化的存储器访问时间无关。

97. 发明申请

US20090235059A1 QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS 有权
标题翻译：基于地址的条件调试指令的资格
公开(公告)号：US20090235059A1
公开(公告)日：2009-09-17
申请号：US12049984
申请日：2008-03-17
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30189
摘要： A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
摘要翻译：处理器实现支持基于其可寻址存储器中的相应地址来选择用于调试指令实例的执行模式可以提供用于以允许指令的某些实例以调试语义来操作的方式来执行调试指令的有吸引力的机制，同时通过执行它们与无操作（NOP）语义。在一些实施例中，可操作执行语义的选择可以基于特定调试指令实例驻留在其中的存储器页的属性。在一些实施例中，可以对地址空间的部分进行限定（例如，使用存储在边界寄存器中的值和特定调试指令实例的地址与定界部分进行比较以选择适当的执行语义在一些实施例中，可以使用两种类型的评估在为特定调试指令实例选择适当的执行语义。

98. 发明申请

US20090213668A1 ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT 有权
标题翻译：可调节管线在存储器电路中
公开(公告)号：US20090213668A1
公开(公告)日：2009-08-27
申请号：US12034888
申请日：2008-02-21
申请人： Shayan Zhang , William C. Moyer , Huy B. Nguyen
发明人： Shayan Zhang , William C. Moyer , Huy B. Nguyen
IPC分类号： G11C7/00
CPC分类号： G06F12/0855 , Y02D10/13
摘要： A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.
摘要翻译：用于操作改善存储器电路的性能的存储器电路和/或用于存储器电路的至少一些操作点的功率消耗的技术包括至少部分地基于存储器的工作点来调节多个操作流水线级。在本发明的至少一个实施例中，用于操作存储器电路的方法包括至少部分地基于由存储器电路产生的反馈信号来选择操作存储器电路的模式。该技术包括基于所选存储器电路的操作模式，使用多个流水线级操作存储器电路。在本发明的至少一个实施例中，该技术包括感测与各个流水线级相关联的定时裕度，并且基于此产生反馈信号。

99. 发明授权

US07574564B2 Replacement pointer control for set associative cache and method 有权
标题翻译：用于设置关联缓存和方法的替换指针控件
公开(公告)号：US07574564B2
公开(公告)日：2009-08-11
申请号：US11382903
申请日：2006-05-11
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0864 , G06F12/126
摘要： A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of sets has a corresponding replacement pointer within the plurality of replacement pointers, and the corresponding replacement pointer indicates a way of the set. A cache command is provided which specifies a set of the plurality of sets and which specifies a replacement way value. In response to the cache command, a current way value of the replacement pointer corresponding to the specified set is replaced with the replacement way value. The cache may further include way locking control circuitry which indicates whether or not one or more ways is locked. By indicating a locked way with the replacement way value, a locked way can be overridden and thus be used for a subsequent cache line fill.
摘要翻译：集合关联高速缓存包括多个集合，其中每个集合具有多个方式。集合关联高速缓存具有多个替换指针，其中多个集合中的每个集合在多个替换指针之间具有对应的替换指针，并且相应的替换指针指示该集合的一种方式。提供了缓存命令，其指定多个集合的集合并且指定替换方式值。响应于缓存命令，与替换方式值替换与指定集合对应的替换指针的当前方式值。高速缓存还可以包括方向锁定控制电路，其指示一个或多个方式是否被锁定。通过用替代方式值指示锁定方式，锁定方式可以被覆盖，从而被用于后续的高速缓存行填充。

100. 发明授权

US07539906B2 System for integrated data integrity verification and method thereof 有权
标题翻译：用于集成数据完整性验证的系统及其方法
公开(公告)号：US07539906B2
公开(公告)日：2009-05-26
申请号：US11094593
申请日：2005-03-30
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.
摘要翻译：根据一种技术，在处理器处接收与处理器和存储器之间的数据传输相关联的第一多个值，并且第一多个值的至少一个子集被累积在一个或多个累加器中。访问一个或多个累加器以获得第一累积值，并将第一累加值与第一预期累加值进行比较。根据第二技术，在处理器处执行第一多个加载操作以访问存储在存储器的第一字段序列中的数据值。数据值被积累在处理器的一个或多个累加器中以产生第一累积值，并且基于第一累积值与第一预期累加值的比较来确定存储器是否已被破坏。

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