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91. 发明申请

WO2018063139A1 TILEABLE ARRAYS OF QUBITS 审中-公开
标题翻译： QUBITS可裁剪阵列
公开(公告)号：WO2018063139A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053866
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： MICHALAK, David J. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi , YOSCOVITS, Zachary R. , CLARKE, James S.
IPC分类号： G06N99/00
CPC分类号： G06N10/00
摘要： Described herein quantum circuit assemblies which include a substrate and a plurality of substantially identical unit cells disposed on a substrate. Each unit cell includes three or more qubits and has a side defined as a "base side." In such an assembly, at least some unit cells are arranged on the substrate so that the base side of each unit cell is aligned along a common straight line, thus creating a row of unit cells defined by the common straight line. Multiple such rows may be provided, each row defined by a different common straight line along which the base sides of the unit cells are aligned. Arranging the qubits in this manner allows providing tileable arrays of qubits, suitable for large-scale manufacturing.
摘要翻译：这里描述的量子电路组件包括衬底和设置在衬底上的多个基本上相同的单元电池。每个单位单元包括三个或更多个量子位并且具有被定义为“基底侧”的一侧。在这样的组件中，至少一些单元电池被布置在基板上，使得每个单元电池的基极侧沿着共同的直线排列，从而形成由共同的直线限定的单元电池行。可以提供多个这样的行，每行由不同的公共直线限定，单位单元的底边沿着该不同的公共直线排列。以这种方式排列量子比特可以提供适合于大规模制造的量子比特阵列。

92. 发明申请

WO2018063138A1 INDEPENDENT DOUBLE-GATE QUANTUM DOT QUBITS 审中-公开
标题翻译：独立的双栅量子点QUBITS
公开(公告)号：WO2018063138A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053861
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , GEORGE, Hubert C. , ROBERTS, Jeanette M. , THOMAS, Nicole K. , CLARKE, James S.
IPC分类号： H01L29/66 , H01L29/12 , H01L29/80
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括基底和远离基底延伸并包括量子阱层的鳍。该装置可以进一步包括设置在鳍状物的第一侧上的第一栅极和设置在鳍状物的不同于第一侧的第二侧上的第二栅极。在鳍的不同侧上提供栅极有利地允许增加可以在鳍中独立地形成和操纵的量子点的数量。如这里详细讨论的，在这样的器件中形成的量子点可以通过一个或多个栅极在x方向上，在鳍方向上在y方向上以及在量子阱层的z方向上被约束。还公开了制造这种装置的方法。

93. 发明申请

WO2018057018A1 QUANTUM DOT ARRAY DEVICES WITH SHARED GATES 审中-公开
标题翻译：量子点阵列器件共享门
公开(公告)号：WO2018057018A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053609
申请日：2016-09-24
申请人： INTEL CORPORATION
发明人： GEORGE, Hubert C. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , CLARKE, James S.
IPC分类号： H01L29/775 , H01L29/12 , H01L29/786 , H01L29/66
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子点器件的量子阱堆叠结构，其中量子阱堆叠结构包括绝缘材料以限定多行量子点形成区域; 和一个延伸到多个行的门。

94. 发明申请

WO2018038707A1 INVERTED MICROSTRIP TRANSMISSION LINES FOR QUBITS 审中-公开
标题翻译：用于QUBITS的反相微带传输线
公开(公告)号：WO2018038707A1
公开(公告)日：2018-03-01
申请号：PCT/US2016/048101
申请日：2016-08-23
申请人： INTEL CORPORATION
发明人： MICHALAK, David J. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi , YOSCOVITS, Zachary R. , CLARKE, James S.
IPC分类号： H01P3/00 , H01P3/08
摘要： Described herein are new transmission line structures, and methods for fabrication thereof, for use as resonators and non-resonant interconnects in quantum circuits. In one aspect of the present disclosure, a proposed transmission line structure includes a substrate, a ground structure disposed over the substrate, and a signal path (i.e. a strip of a conductive material, preferably a superconductive material) suspended over the ground structure and supported by a signal path support layer. The proposed structure further includes an opening in the signal path support layer, the opening being indicative of using the fabrication process described herein for forming the proposed structure. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits.
摘要翻译：这里描述的是新的传输线结构及其制造方法，用作量子电路中的谐振器和非谐振互连。在本公开的一个方面中，提出的传输线结构包括衬底，设置在衬底上的接地结构以及悬挂在接地结构上并且被支撑的信号路径（即，导电材料的条带，优选超导材料的条带）由信号路径支持层。所提出的结构还包括信号路径支撑层中的开口，该开口指示使用本文所述的制造工艺来形成所提出的结构。这里提出的传输线结构可以用于提供去往，来自，或者和/或在量子位之间的微波连接，或者设置解决单个量子位的频率。

95. 发明申请

WO2018004554A1 QUANTUM DOT DEVICES WITH MODULATION DOPED STACKS 审中-公开
标题翻译：具有调制掺杂堆叠的量子点器件
公开(公告)号：WO2018004554A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/039953
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： MICHALAK, David J. , PILLARISETTY, Ravi , LE, Van H. , ROBERTS, Jeanette M. , CLARKE, James S. , YOSCOVITS, Zachary R.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠，其包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 以及设置在量子阱堆叠之上的栅极。掺杂层可以包括第一材料和掺杂剂，第一材料可以具有掺杂剂的第一扩散率，阻挡层可以包括具有掺杂剂的第二扩散率的第二材料，并且第二扩散率可以小于第一扩散率。

96. 发明申请

WO2017213647A1 QUANTUM DOT DEVICES WITH BACK GATES 审中-公开
标题翻译：量子点设备与后门
公开(公告)号：WO2017213647A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036568
申请日：2016-06-09
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S. , LE, Van H.
IPC分类号： H01L29/66 , H01L29/778 , H01L29/12
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：衬底和设置在衬底上的量子阱堆叠。量子阱堆可以包括量子阱层和背栅，并且背栅可以设置在量子阱层和衬底之间。

97. 发明申请

WO2017213646A1 QUANTUM DOT DEVICES WITH MODULATION DOPED STACKS 审中-公开
标题翻译：具有调制掺杂堆叠的量子点器件
公开(公告)号：WO2017213646A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036565
申请日：2016-06-09
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S. , LE, Van H.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12 , H01L29/80
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. In some embodiments, a quantum dot device may include: a fin extending away from a base and having insulating material disposed on at least two opposing faces of the fin, wherein the fin includes a quantum well stack and the quantum well stack includes a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠，其包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 以及设置在量子阱堆叠之上的栅极。在一些实施例中，量子点器件可以包括：远离基底延伸并且具有设置在鳍的至少两个相对面上的绝缘材料的鳍，其中鳍包括量子阱堆，并且量子阱堆包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 和设置在量子阱堆叠之上的栅极。

98. 发明申请

WO2017213640A1 QUANTUM DOT DEVICES 审中-公开
标题翻译：量子点设备
公开(公告)号：WO2017213640A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036324
申请日：2016-06-08
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S.
IPC分类号： H01L29/778 , H01L29/12 , H01L29/66 , H01L29/80 , H01L29/78
CPC分类号： H01L29/127 , B82Y10/00 , B82Y40/00 , H01L21/28088 , H01L21/3212 , H01L29/0673 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/4966 , H01L29/66431 , H01L29/6656 , H01L29/66795 , H01L29/66977 , H01L29/7613 , H01L29/778 , H01L29/7781 , H01L29/7782 , H03K17/687
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：基座; 延伸离开所述基部的鳍片，其中所述鳍片包括量子阱层; 以及设置在翅片上的一个或多个闸门。在一些这样的实施例中，一个或多个门可以包括第一，第二和第三门。间隔物可以设置在第一和第二栅极的侧面上，使得第一间隔物设置在第一栅极的靠近第二栅极的一侧上，并且与第一间隔物物理分离的第二间隔物设置在第一第二门的靠近第一门的一侧。第三栅极可以设置在第一和第二栅极之间的鳍片上并且在第一和第二间隔器之间延伸。

99. 发明申请

WO2017213637A1 QUANTUM DOT DEVICES WITH PATTERNED GATES 审中-公开
标题翻译：量子点装置图案化门
公开(公告)号：WO2017213637A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036315
申请日：2016-06-08
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , ROBERTS, Jeanette M. , GEORGE, Hubert C. , CLARKE, James S. , THOMAS, Nicole K.
IPC分类号： H01L29/778 , H01L29/80 , H01L29/12 , H01L29/66
CPC分类号： H01L29/66431 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66977 , H01L29/7613 , H01L29/7781 , H01L29/7782 , H01L29/785
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠; 设置在量子阱堆叠上的多个第一栅极; 多对隔离物，每对隔离物设置在相关联的第一门的相对侧上，其中一对隔离物中的每个隔离物具有弯曲的表面，所述弯曲表面远离相关联的第一门; 以及设置在量子阱堆叠上的多个第二栅极，其中每个间隔物的弯曲表面与第二栅极中的一个相邻，使得每个第二栅极的至少一部分与相邻间隔物的弯曲表面互补地成形。

100. 发明申请

WO2016175782A1 MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：微电子导电路线及其制造方法
公开(公告)号：WO2016175782A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028209
申请日：2015-04-29
申请人： INTEL CORPORATION , CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
发明人： CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L2221/1063
摘要： A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
摘要翻译：可以形成包括导电迹线和导电通孔的导电路径结构，其中导电通孔直接接触导电迹线。在一个实施例中，可以通过在导电迹线上形成介电材料层来形成导电路径结构。可以通过介电材料层形成通孔开口以暴露导电迹线的一部分，并且阻挡层可以仅来自导电迹线的暴露部分。可以在通孔开口的侧壁上形成阻挡线，然后可以去除阻挡层。然后可以在通孔开口内形成导电通孔，其中导电通孔直接接触导电迹线。

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