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91. 发明申请

WO2018174932A1 SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE 审中-公开
公开(公告)号：WO2018174932A1
公开(公告)日：2018-09-27
申请号：PCT/US2017/040543
申请日：2017-07-01
申请人： INTEL CORPORATION
发明人： VALENTINE, Robert , ADELMAN, Menachem , OULD-AHMED-VALL, Elmoustapha , TOLL, Bret L. , GIRKAR, Milind B. , SPERBER, Zeev , CHARNEY, Mark J. , RAPPOPORT, Rinat , CORBAL, Jesus , SHWARTSMAN, Stanislav , YANOVER, Igor , HEINECKE, Alexander, F. , ZIV, Barukh , BAUM, Daniel , GEBIL, Yuri
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

92. 发明申请

WO2018111228A1 APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2018111228A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066242
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

93. 发明申请

WO2017112308A1 FLOATING POINT (FP) ADD LOW INSTRUCTIONS FUNCTIONAL UNIT 审中-公开
标题翻译：浮点（FP）添加低指令功能单元
公开(公告)号：WO2017112308A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063634
申请日：2016-11-23
申请人： INTEL CORPORATION
发明人： ANDERSON, Cristina S. , CORNEA-HASEGAN, Marius A. , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , ASTAFEV, Nikita , CHARNEY, Mark J. , GIRKAR, Milind B. , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
IPC分类号： G06F9/30
CPC分类号： G06F7/485
摘要： An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.
摘要翻译：示例处理器包括寄存器和ADD低功能单元。该寄存器存储第一，第二和第三浮点（FP）值。 ADD低功能单元接收执行ADD低操作的请求，并且响应于该请求：将第一FP值与第二FP值相加以获得第一总和值; 将第一个总和值舍入以生成ADD值; 将第一FP值与第二FP值相加以获得第二和值; 从第二和值中减去ADD值以生成差值; 归一化差值以获得归一化差值; 舍入归一化差值以生成ADD低值; 并将ADD低值发送给应用程序。

94. 发明申请

WO2017112175A1 INSTRUCTIONS AND LOGIC FOR LOAD-INDICES-AND-SCATTER OPERATIONS 审中-公开
标题翻译：负载指数和散射操作的指令和逻辑
公开(公告)号：WO2017112175A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062705
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： GOKHALE, Indraneil M. , YOUNT, Charles R. , VALLES, Antonio C. , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/44 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30101 , G06F9/3016 , G06F12/084 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/1027 , G06F2212/452
摘要： A processor includes an execution unit to execute instructions to load indices from an array of indices and scatter elements to locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be scattered by the instruction, as needed, an index value to be used in computing the address in memory at which a particular data element is to be written. The index values may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction and the index values retrieved for the data element locations, with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction and store them to the computed locations.
摘要翻译：处理器包括执行单元以执行指令以从指数阵列加载指数并基于这些指数将元素散布到稀疏存储器中的位置。执行单元包括用于对于要由指令散布的每个数据元素根据需要加载用于计算存储器中的地址的索引值的逻辑，在该地址处将写入特定的数据元素。索引值可以从为该指令识别的索引数组中检索。执行单元包括用于基于为指令指定的基地址和为数据元素位置检索的索引值的总和来计算地址的逻辑，其具有可选的缩放。执行单元包括从指定的指令源矢量寄存器中的连续位置检索数据元素并将它们存储到计算出的位置的逻辑。

95. 发明申请

WO2017105719A1 INSTRUCTIONS AND LOGIC FOR BLEND AND PERMUTE OPERATION SEQUENCES 审中-公开
标题翻译：混合和强制操作顺序的说明和逻辑
公开(公告)号：WO2017105719A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061965
申请日：2016-11-15
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , HUH, Joonmoo
IPC分类号： G06F15/80
CPC分类号： G06F9/30029 , G06F9/30 , G06F9/30036 , G06F9/30101 , G06F9/3016
摘要： A processor includes a core to execute an instruction and logic to determine that the instruction will require strided data converted from source data in memory. The strided data is to include corresponding indexed elements from structures in the source data to be loaded into a same register to be used to execute the instruction. The core also includes logic to load source data into preliminary vector registers. The source data is to be unaligned as resident in the vector registers. The core includes logic to apply blend instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the plurality of structures to be loaded into respective interim vector registers, and to apply further blend instructions to contents of the interim vector registers to cause additional indexed elements from the structures to be loaded into respective source vector registers.
摘要翻译：处理器包括执行指令和逻辑以确定该指令将需要从存储器中的源数据转换的分步数据的核心。被解压缩的数据将包括来自源数据中的结构的对应索引元素以被加载到用于执行指令的相同寄存器中。内核还包含将源数据加载到初始向量寄存器的逻辑。源数据将作为驻留在矢量寄存器中的对齐方式。内核包括用于将混合指令应用于初步向量寄存器的内容以使得来自多个结构的对应索引元素被加载到相应临时向量寄存器中并且将进一步混合指令应用于临时向量寄存器的内容以导致额外来自结构的索引元素被加载到相应的源向量寄存器中。

96. 发明申请

WO2017105714A1 INSTRUCTION AND LOGIC FOR SECURE INSTRUCTION EXECUTION PIPELINE 审中-公开
标题翻译：用于安全指令执行管道的指令和逻辑
公开(公告)号：WO2017105714A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061957
申请日：2016-11-15
申请人： INTEL CORPORATION
发明人： DESAI, Imran , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/30
CPC分类号： G06F12/1408 , G06F9/30029 , G06F9/3016 , G06F9/30178 , G06F12/0875 , G06F12/1009 , G09C1/00 , H04L9/003 , H04L2209/04 , H04L2209/16
摘要： A processor includes a front end to receive an encrypted instruction sequence. The processor also includes a decoder including logic to identify a encrypted command from a packet in the encrypted instruction sequence, logic to identify a key index from the packet, logic to determine an encrypted opcode lookup table with the key index, logic to look up a decoded opcode from the encrypted opcode lookup table based upon the key index, and logic to forward the decoded opcode for execution.
摘要翻译：处理器包括接收加密指令序列的前端。该处理器还包括解码器，该解码器包括用于从加密指令序列中的分组中识别加密命令的逻辑，用于从分组中识别密钥索引的逻辑，用密钥索引确定加密操作码查找表的逻辑，根据密钥索引从加密操作码查找表中解码操作码，以及转发解码操作码以供执行的逻辑。

97. 发明申请

WO2017105712A1 INSTRUCTION AND LOGIC FOR PERMUTE SEQUENCE 审中-公开
标题翻译：用于伪序列的指令和逻辑
公开(公告)号：WO2017105712A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061954
申请日：2016-11-15
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , HUH, Joonmoo
IPC分类号： G06F9/30 , G06F9/345 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30 , G06F9/30101 , G06F9/3016 , G06F12/0875 , G06F2212/452
摘要： A processor includes a core to execute an instruction and logic to determine that the instruction will require strided data converted from source data in memory. The strided data is to include corresponding indexed elements from structures in the source data to be loaded into a final register to be used to execute the instruction. The core also includes logic to load source data into a plurality of preliminary vector registers to align a defined element of one of the preliminary vector registers in a position that corresponds to a required position in the final register for execution. The core includes logic to apply permute instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the structures to be loaded into respective source vector registers.
摘要翻译：处理器包括执行指令和逻辑以确定该指令将需要从存储器中的源数据转换的分步数据的核心。被解压缩的数据将包括来自源数据中的结构的对应索引元素以加载到用于执行指令的最终寄存器中。核心还包括用于将源数据加载到多个初始向量寄存器中以将初始向量寄存器之一的定义的元素对准在与用于执行的最终寄存器中的所需位置相对应的位置中的逻辑。核心包括将置换指令应用于初步向量寄存器的内容以使来自结构的对应索引元素被加载到相应源向量寄存器中的逻辑。

98. 发明申请

WO2016105819A1 METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE 审中-公开
标题翻译：用于执行矢量位开关的方法和装置
公开(公告)号：WO2016105819A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062564
申请日：2015-11-25
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , VALENTINE, Robert , CHARNEY, Mark J. , SOLE, Guillem , ESPASA, Roger
IPC分类号： G06F9/30
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3012 , G06F15/8076
摘要： An apparatus and method for performing a vector bit shuffle. For example, one embodiment of a processor comprises: a first vector register to store a plurality of source data elements; a second vector register to store a plurality of control elements, each of the control elements comprising a plurality of bit fields, each bit field to be associated with a corresponding bit position in a destination mask register and to identify a bit from each of the source data elements to be copied to each of the particular bit positions; and vector bit shuffle logic to read each bit field from the second vector register to identify a bit from each of the source data elements and to responsively copy the bit from each of the source data elements to each of the corresponding bit positions in the destination mask register.
摘要翻译：用于执行向量比特洗牌的装置和方法。例如，处理器的一个实施例包括：第一向量寄存器，用于存储多个源数据元素; 用于存储多个控制元件的第二矢量寄存器，每个控制元件包括多个位域，每个位字段将与目的地掩模寄存器中的相应位位置相关联，并且从源中的每一个识别位要复制到每个特定位位置的数据元素; 以及向量位洗牌逻辑，以从第二向量寄存器读取每个位域，以识别来自每个源数据元素的位，并且响应地将每个源数据元素中的位复制到目标掩码中的每个相应位位置寄存器。

99. 发明申请

WO2016105800A1 SYSTEMS, APPARATUSES, AND METHODS FOR DATA SPECULATION EXECUTION 审中-公开
标题翻译：用于数据规范执行的系统，设备和方法
公开(公告)号：WO2016105800A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062299
申请日：2015-11-24
申请人： INTEL CORPORATION
发明人： HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , GIRKAR, Milind B.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3842
摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for DSX comprises execution hardware to execute instructions to begin and end a data speculative execution (DSX) and speculative instructions during the DSX, and DSX tracking hardware to track speculative memory accesses and detect ordering violations in a DSX of speculative instructions using a sequence number, addresses of instruction accesses, and whether an instruction being tracked is a write, and to trigger a mis-speculation upon an ordering violation.
摘要翻译：描述用于数据推测执行（DSX）的系统，方法和装置。在一些实施例中，用于DSX的硬件装置包括执行硬件以执行在DSX期间开始和结束数据推测执行（DSX）和推测指令的指令，以及DSX跟踪硬件以跟踪推测性存储器访问并检测DSX中的排序违规使用序列号，指令访问地址以及正在跟踪的指令是否为写入的推测性指令，以及在排序违规时触发错误猜测。

100. 发明申请

WO2016105766A1 APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION 审中-公开
标题翻译：矢量水平逻辑指导的装置和方法
公开(公告)号：WO2016105766A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062095
申请日：2015-11-23
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , ESPASA, Roger , GUILLEN, David F. , SANCHEZ, F. Jesus , SOLE, Guillem
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30167 , G06F9/34
摘要： An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.
摘要翻译：描述了用于执行向量水平逻辑指令的装置和方法。例如，处理器的一个实施例包括：从存储器取出指令的获取逻辑，以及执行逻辑，用于从立即操作数的第一指定位组确定一个或多个数据元素的第一集合的值，其中位置从所述立即操作数的所述第一指定位组确定的所述第一组一个或多个数据元素是基于与第一组的打包数据元素相对应的最高有效位的第一组一个或多个索引值目的地打包数据操作数的一个或多个位置，并且具有对应于第一源打包数据操作数的对应位置处的数据元素的最低有效位。

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