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91. 发明授权

US07791112B2 Channel stress engineering using localized ion implantation induced gate electrode volumetric change 失效
标题翻译：通道应力工程采用局部离子注入诱导栅电极体积变化
公开(公告)号：US07791112B2
公开(公告)日：2010-09-07
申请号：US11867264
申请日：2007-10-04
申请人： Zhjiong Luo , Huilong Zhu
发明人： Zhjiong Luo , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28061 , H01L29/4941 , H01L29/517 , H01L29/7833 , H01L29/7845
摘要： A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electrode located over the channel region within the semiconductor substrate. The volume changed portion of the gate electrode is typically bidirectionally symmetrically graded in a vertical direction. The volume-changed portion of the gate electrode has a first stress that induces a second stress different than the first stress into the channel region of the semiconductor substrate.
摘要翻译：制造半导体结构的方法使用注入到位于半导体衬底内的沟道区域上的栅电极的体积变化部分中的体积变化离子，以形成位于该半导体衬底内的沟道区域上方的栅电极的体积变化部分半导体衬底。栅电极的体积变化部分通常在垂直方向上双向对称地分级。栅电极的体积变化部分具有在半导体衬底的沟道区域中产生不同于第一应力的第二应力的第一应力。

92. 发明授权

US07790581B2 Semiconductor substrate with multiple crystallographic orientations 有权
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US07790581B2
公开(公告)日：2010-09-07
申请号：US11306713
申请日：2006-01-09
申请人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
发明人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L21/20 , H01L21/36 , H01L21/00
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/0649 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78687
摘要： A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
摘要翻译：一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。该方法提供了在半导体衬底上外延生长半导体层以封装介电层。该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

93. 发明授权

US07767503B2 Hybrid SOI/bulk semiconductor transistors 失效
标题翻译：混合SOI /体半导体晶体管
公开(公告)号：US07767503B2
公开(公告)日：2010-08-03
申请号：US12132853
申请日：2008-06-04
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

94. 发明授权

US07741658B2 Self-aligned super stressed PFET 有权
标题翻译：自对准超应力PFET
公开(公告)号：US07741658B2
公开(公告)日：2010-06-22
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L31/0328
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

95. 发明授权

US07723750B2 MOSFET with super-steep retrograded island 失效
标题翻译：具超级陡峭退火岛的MOSFET
公开(公告)号：US07723750B2
公开(公告)日：2010-05-25
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L29/737
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

96. 发明授权

US07709333B2 Method for reducing overlap capacitance in field effect transistors 失效
标题翻译：降低场效应晶体管重叠电容的方法
公开(公告)号：US07709333B2
公开(公告)日：2010-05-04
申请号：US12173098
申请日：2008-07-15
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
摘要翻译：场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域仅沿着栅极导体的宽度的选定位置。

97. 发明授权

US07696574B2 Semiconductor substrate with multiple crystallographic orientations 失效
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US07696574B2
公开(公告)日：2010-04-13
申请号：US11163652
申请日：2005-10-26
申请人： Huilong Zhu
发明人： Huilong Zhu
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： A semiconductor structure and its method for fabrication include a first surface semiconductor layer of a first crystallographic orientation located upon a dielectric surface of a substrate. Located laterally separated upon the dielectric surface from the first surface semiconductor layer is a stack layer. The stack layer includes a buried semiconductor layer located nearer the dielectric surface and a second surface semiconductor layer of a second crystallographic orientation different from the first crystallographic orientation located over and not contacting the buried semiconductor layer. The semiconductor structure provides a pair of semiconductor surface regions of different crystallographic orientation. A particular embodiment may be fabricated utilizing a sequential laminating, patterning, selective stripping and selective epitaxial deposition method.
摘要翻译：半导体结构及其制造方法包括位于基板的电介质表面上的第一晶体取向的第一表面半导体层。在第一表面半导体层的电介质表面上横向分离的是堆叠层。堆叠层包括位于电介质表面附近的掩埋半导体层，以及不同于位于掩埋半导体层之上并且不与埋入半导体层接触的第一晶体取向的第二晶体取向的第二表面半导体层。半导体结构提供了一对具有不同晶体取向的半导体表面区域。可以使用顺序层压，图案化，选择性剥离和选择性外延沉积方法来制造特定实施例。

98. 发明授权

US07696040B2 Method for fabrication of fin memory structure 失效
标题翻译：翅片存储器结构的制造方法
公开(公告)号：US07696040B2
公开(公告)日：2010-04-13
申请号：US11755246
申请日：2007-05-30
申请人： Huilong Zhu
发明人： Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1211 , H01L21/845 , H01L27/0207 , H01L27/10838 , H01L27/10876 , H01L27/10879 , H01L27/10888 , H01L29/66795 , H01L29/785
摘要： A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.
摘要翻译：半导体鳍片存储器结构和半导体鳍片存储器结构的制造方法包括在finFET结构内的半导体鳍片沟道，其与鳍式鳍片FET集成的鳍式电容器结构内的导体鳍状电容器节点相邻并且更薄结构体。可以适当地处理单个半导体层以在finFET结构内提供与鳍式电容器结构内的导体鳍状电容器节点相邻并且更薄的半导体鳍状沟道。

99. 发明授权

US07691690B2 Methods for forming dual fully silicided gates over fins of FinFet devices 有权
标题翻译：在FinFet设备的翅片上形成双完全硅化栅的方法
公开(公告)号：US07691690B2
公开(公告)日：2010-04-06
申请号：US11622586
申请日：2007-01-12
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes forming a metal layer over both fins and annealing the FinFet device to form fully silicided gates over each fin of the FinFet device.
摘要翻译：公开了在FinFet装置的翅片上形成完全硅化栅的方法。本公开提供了用于从多晶硅层和多晶硅锗层在每个鳍上形成栅叠层的方法，然后在一个鳍上去除多晶硅锗层。本公开还包括在两个翅片上形成金属层并退火FinFet器件以在FinFet器件的每个鳍上形成完全硅化的栅极。

100. 发明授权

US07646039B2 SOI field effect transistor having asymmetric junction leakage 失效
标题翻译：具有不对结结泄漏的SOI场效应晶体管
公开(公告)号：US07646039B2
公开(公告)日：2010-01-12
申请号：US11830972
申请日：2007-07-31
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7843 , H01L21/26506 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/205 , H01L29/26 , H01L29/267 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/78654
摘要： A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.
摘要翻译：源极沟槽和漏极沟槽在包括半导体衬底中的第一半导体的顶部半导体层中不对称地形成。在源极沟槽和漏极沟槽中沉积具有比第一半导体材料窄的带隙的第二半导体材料，以分别形成源极窄带隙区域和漏极侧窄带隙区域。形成栅极间隔物，并且在顶部半导体层中形成源区和漏极区。扩展源极区域和延伸体区域之间的边界的一部分形成在源极窄带隙区域中。由于与第一半导体材料的带隙相比，第二半导体材料的带隙较窄，所以形成在扩展体区域中的电荷通过源放电，并且减少或消除浮体效应。

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