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91. 发明授权

US08176263B2 Memory management apparatus and method for same 有权
标题翻译：内存管理装置及方法相同
公开(公告)号：US08176263B2
公开(公告)日：2012-05-08
申请号：US12076021
申请日：2008-03-13
申请人： Kenji Yamada , Hideaki Ishihara
发明人： Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
摘要： A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus.
摘要翻译：存储器管理装置使用链路列表存储器来管理数据存储器的使用区域和空闲区域。通过多个端口中的每一个使用数据存储器的使用区域被限制，并且数据存储器的使用区域被配置为总是为多个端口中的每个端口提供。以这种方式，防止了特定端口对数据存储器的垄断使用，并且在存储器管理装置的控制下，多个端口中的每一个被牢固地设置有数据存储器的使用区域。

92. 发明授权

US08046615B2 Microcomputer system with reduced power consumption 有权
标题翻译：微电脑系统功耗降低
公开(公告)号：US08046615B2
公开(公告)日：2011-10-25
申请号：US12285481
申请日：2008-10-07
申请人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
发明人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , Y02D10/122 , Y02D10/126
摘要： A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.
摘要翻译：除了具有主CPU的主微型计算机之外，还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。当主CPU向子CPU发出操作停止通知时，子CPU识别通知，停止对主微型计算机的供电，并将子时钟部分设置为间歇模式。子CPU确定在间歇模式的周期内操作状态条件满足，子CPU将副时钟部分切换为连续模式，以重新开始向主微型计算机供电。

93. 发明授权

US07991982B2 Microcomputer and encoding system for executing peripheral function instructions 有权
标题翻译：用于执行外围功能指令的微机和编码系统
公开(公告)号：US07991982B2
公开(公告)日：2011-08-02
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

94. 发明授权

US07906946B2 Semiconductor integrated circuit device for providing series regulator 有权
标题翻译：用于提供串联调节器的半导体集成电路器件
公开(公告)号：US07906946B2
公开(公告)日：2011-03-15
申请号：US12076451
申请日：2008-03-19
申请人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译：提供一种用于控制外部输出晶体管的半导体集成电路器件。所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。

95. 发明授权

US07900081B2 Microcomputer and control system having the same 有权
标题翻译：微电脑和控制系统具有相同的功能
公开(公告)号：US07900081B2
公开(公告)日：2011-03-01
申请号：US11878799
申请日：2007-07-26
申请人： Chikara Kobayashi , Shinichirou Taguchi , Yoshinori Gotoh , Youichi Fujita , Hideaki Ishihara
发明人： Chikara Kobayashi , Shinichirou Taguchi , Yoshinori Gotoh , Youichi Fujita , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.
摘要翻译：微型计算机包括用于产生和输出主时钟信号的主振荡器，用于产生和输出子时钟信号的子振荡器，基于主时钟信号操作的中央处理单元，基于子时钟信号操作的信号输出电路时钟信号并以预定间隔输出定时信号，以及电压监视电路，其基于子时钟信号进行操作，并且响应于定时信号间歇地执行电压监视功能。子振荡器独立于主振荡器工作。

96. 发明授权

US07889228B2 Signal processing device for endoscope 有权
标题翻译：内窥镜信号处理装置
公开(公告)号：US07889228B2
公开(公告)日：2011-02-15
申请号：US11497742
申请日：2006-08-02
申请人： Hideaki Ishihara , Takayuki Hanawa , Nobuyuki Doguchi , Fumiyuki Okawa
发明人： Hideaki Ishihara , Takayuki Hanawa , Nobuyuki Doguchi , Fumiyuki Okawa
IPC分类号： H04N7/18 , A61B1/04
CPC分类号： H04N5/361 , A61B1/00006 , A61B1/00009 , A61B1/051 , G02B23/2476 , H01L27/148 , H04N5/367 , H04N5/372 , H04N5/37213 , H04N2005/2255
摘要： An endoscope includes a solid image-pickup device having an image area and an optical black area for performing photoelectric conversion and including a function of varying an amplification ratio, and a first signal clamp circuit clamps the analog output signal that is outputted from the solid image-pickup device to adjust into an input range of the analog signal processing circuit with an analog reference signal which is unaffected by a defective pixel in the optical black area. The clamped signal is processed to extract signal components which are photoelectrically converted by the analog signal processing circuit by the image area. The output signal from the analog signal processing circuit clamps the signal in the optical black area by using output signals of at least the number of pixels larger than the number of pixels in a horizontal direction in the optical black area by the second signal clamp circuit.
摘要翻译：内窥镜包括具有用于进行光电转换并具有变化放大率的功能的图像区域和光学黑色区域的固体摄像装置，并且第一信号钳位电路钳位从实心图像输出的模拟输出信号以使用不受光学黑色区域中的缺陷像素影响的模拟参考信号来调整到模拟信号处理电路的输入范围。处理钳位信号以提取由模拟信号处理电路通过图像区域光电转换的信号分量。来自模拟信号处理电路的输出信号通过使用比第二信号钳位电路在光学黑色区域中的水平方向上的像素数量的至少大的像素的数量的输出信号来将光信号中的信号钳位在光学黑色区域中。

97. 发明授权

US07664933B2 Microcomputer and encoding system for instruction code and CPU 有权
公开(公告)号：US07664933B2
公开(公告)日：2010-02-16
申请号：US11330237
申请日：2006-01-12
申请人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
发明人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.

98. 发明申请

US20090009211A1 Microcomputer and functional evaluation chip 有权
标题翻译：微电脑和功能评估芯片
公开(公告)号：US20090009211A1
公开(公告)日：2009-01-08
申请号：US12155017
申请日：2008-05-29
申请人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
发明人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
IPC分类号： H03K19/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译：根据操作模式起作用的微计算机包括：对施加到模式设置终端的信号中的电平变化次数进行计数的模式计数器; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。在测试模式下，能够从外部电路输入测试指令数据。

99. 发明授权

US07444529B2 Microcomputer having rewritable nonvolatile memory 失效
标题翻译：微计算机具有可重写的非易失性存储器
公开(公告)号：US07444529B2
公开(公告)日：2008-10-28
申请号：US11238106
申请日：2005-09-29
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。

100. 发明授权

US07356721B2 Microcomputer and emulation apparatus 有权
标题翻译：微电脑和仿真设备
公开(公告)号：US07356721B2
公开(公告)日：2008-04-08
申请号：US11007298
申请日：2004-12-09
申请人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
发明人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
IPC分类号： G06F1/12 , G06F9/455
CPC分类号： G06F13/24
摘要： A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.
摘要翻译：单片微计算机包括逻辑电路，CPU和触发器，用于基于时钟信号将由逻辑电路提供的中断请求信号同步到CPU。多芯片仿真装置包括分别用于仿真逻辑电路，CPU和触发器的功能的外围评估芯片，CPU评估芯片和装置。当在开发中使用多芯片仿真装置来模拟单片机的功能时，用于模拟触发器的功能的装置同步中断请求信号以吸收由中断请求信号引起的延迟时间由于外围评估芯片和CPU评估芯片之间的物理距离，使得仿真中的中断处理定时与单片机的实际操作中的中断处理定时相匹配。

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