专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08559736B2 Image decoding apparatus, image coding apparatus, image decoding circuit, and image decoding method 有权
标题翻译：图像解码装置，图像编码装置，图像解码电路以及图像解码方法
公开(公告)号：US08559736B2
公开(公告)日：2013-10-15
申请号：US13321857
申请日：2011-03-16
申请人： Hiroshi Amano , Takeshi Tanaka , Takashi Hashimoto , Yoshiteru Hayashi
发明人： Hiroshi Amano , Takeshi Tanaka , Takashi Hashimoto , Yoshiteru Hayashi
IPC分类号： H04N7/50
CPC分类号： H04N19/60 , H04N19/122 , H04N19/44 , H04N19/547
摘要： A decoding apparatus (100) according to the present invention includes: a decoding unit (101) which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit (110) accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit (103) storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit (112) which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit (102) which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit (110) to the orthogonal transfer basis storage unit (103) only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency.
摘要翻译：根据本发明的解码装置（100）包括：解码单元（101），其对识别用于逆正交变换的正交变换基准的识别信息进行解码; 正交变换基积累单元（110），累积用于逆正交变换的正交变换基; 正交变换基准存储单元，从存储的正交变换基中存储用于逆变换的正交变换基础; 使用所识别的正交变换基础进行逆正交变换的逆正交变换单元（112）以及正交变换基传送控制单元（102），其仅在所识别的正交变换基础尚未存储时，将所识别的正交传送基础从正交变换基础累积单元（110）传送到正交传送基础存储单元（103）。利用这种结构，可以减少存储正交变换基础和存储器访问延迟的存储器的存储器带宽。

92. 发明授权

US08497547B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08497547B2
公开(公告)日：2013-07-30
申请号：US13591035
申请日：2012-08-21
申请人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
发明人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
IPC分类号： H01L27/115
CPC分类号： H01L29/7885 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328
摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
摘要翻译：提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。存储栅电极的高度低于控制栅电极的高度。在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。

93. 发明申请

US20120306051A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTORING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120306051A1
公开(公告)日：2012-12-06
申请号：US13587008
申请日：2012-08-16
申请人： Yoshiyuki Kawashima , Koichi Toba , Yasushi Ishii , Toshikazu Matsui , Takashi Hashimoto
发明人： Yoshiyuki Kawashima , Koichi Toba , Yasushi Ishii , Toshikazu Matsui , Takashi Hashimoto
IPC分类号： H01L27/08
CPC分类号： H01L28/60 , H01L27/0629 , H01L27/0805 , H01L27/105 , H01L27/10805 , H01L27/11526 , H01L27/11531 , H01L27/11573 , H01L28/40
摘要： In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
摘要翻译：关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。电容器元件形成在半导体衬底上形成的元件隔离区域中。电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。

94. 发明授权

US08309876B2 Electric discharge machining apparatus and electric discarge machining method 有权
标题翻译：放电加工装置和电动放大加工方法
公开(公告)号：US08309876B2
公开(公告)日：2012-11-13
申请号：US12865655
申请日：2008-01-31
申请人： Takashi Hashimoto , Takashi Yuzawa , Koichiro Hattori , Yoshikazu Ukai
发明人： Takashi Hashimoto , Takashi Yuzawa , Koichiro Hattori , Yoshikazu Ukai
IPC分类号： B23H1/00
CPC分类号： B23H1/022
摘要： In a waveform of switching signals, which is output from a full-bridge circuit formed of four switching elements, includes a normal polarity pulse group and a reversed polarity pulse group for controlling an output timing of voltage pulses. A duty cycle of the normal polarity pulse group containing a plurality of normal polarity pulses, which apply a positive power-supply polarity to a workpiece and apply a negative power-supply polarity to a machining-purpose electrode, is configured so as to be different from a duty cycle of the reversed polarity pulse group containing a plurality of reversed polarity pulses, which apply a negative power-supply polarity to the workpiece and apply a positive power-supply polarity to the machining-purpose electrode.
摘要翻译：在从由四个开关元件构成的全桥电路输出的开关信号的波形中，包括用于控制电压脉冲的输出定时的正极性脉冲组和反极性脉冲组。将包含对工件施加正电源极性并向加工用电极施加负电源极性的多个正常极性脉冲的正常极性脉冲群的占空比构成为不同从包含多个反极性脉冲的反极性脉冲组的占空比，向工件施加负电源极性，并向加工用电极施加正电源极性。

95. 发明授权

US08278169B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08278169B2
公开(公告)日：2012-10-02
申请号：US12885086
申请日：2010-09-17
申请人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Takashi Hashimoto , Kosuke Okuyama
发明人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Takashi Hashimoto , Kosuke Okuyama
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
摘要翻译：本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。

96. 发明授权

US08269266B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08269266B2
公开(公告)日：2012-09-18
申请号：US12825147
申请日：2010-06-28
申请人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
发明人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
IPC分类号： H01L27/115
CPC分类号： H01L29/7885 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328
摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
摘要翻译：提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。存储栅电极的高度低于控制栅电极的高度。在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。

97. 发明申请

US20120132978A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20120132978A1
公开(公告)日：2012-05-31
申请号：US13302184
申请日：2011-11-22
申请人： Koichi TOBA , Yasushi Ishi , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
发明人： Koichi TOBA , Yasushi Ishi , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
IPC分类号： H01L29/788 , H01L21/28 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11573 , H01L29/42344 , H01L29/792
摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
摘要翻译：提供了具有非易失性存储器的半导体器件，其具有改进的特性。半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

98. 发明授权

US08054680B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08054680B2
公开(公告)日：2011-11-08
申请号：US10852150
申请日：2004-05-25
申请人： Nozomu Matsuzaki , Tetsuya Ishimaru , Makoto Mizuno , Takashi Hashimoto
发明人： Nozomu Matsuzaki , Tetsuya Ishimaru , Makoto Mizuno , Takashi Hashimoto
IPC分类号： G11C11/34 , G11C7/00 , H01L29/792
CPC分类号： G11C16/107 , G11C16/3468
摘要： Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.
摘要翻译：通过从基板注入电子并将电子提取到栅极电极进行擦除和写入操作的存储单元构成半导体非易失性存储器件。这是一个栅极提取半导体非易失性存储器件。在该器件中，如果在擦除和写入操作的第一过程中施加擦除偏置，则发生过度过热状态的存储器单元，并且这种存储器单元的电荷保留特性降低。本发明提供一种半导体非易失性存储器件，其使用在施加擦除偏置之前将所有存储单元写入擦除单元的装置，然后施加擦除偏置。

99. 发明申请

US20110235716A1 DECODING APPARATUS, DECODING METHOD, PROGRAM AND INTEGRATED CIRCUIT 审中-公开
标题翻译：解码设备，解码方法，程序和集成电路
公开(公告)号：US20110235716A1
公开(公告)日：2011-09-29
申请号：US13121041
申请日：2010-10-07
申请人： Takeshi Tanaka , Hiroshi Amano , Yoshiteru Hayashi , Takashi Hashimoto , Satoshi Kajita
发明人： Takeshi Tanaka , Hiroshi Amano , Yoshiteru Hayashi , Takashi Hashimoto , Satoshi Kajita
IPC分类号： H04N7/26
CPC分类号： H04N19/433 , H04N19/44
摘要： A decoding apparatus (100) includes: a first memory unit (20) storing pixel data of a decoded reference image to be referred to in decoding; a second memory unit (30) having a storage capacity smaller than that of the first memory unit (20) and providing a data reading speed faster than that provided by the first memory unit (20); a search area transfer unit (40) transferring, from the first memory unit (20) to the second memory unit (30), pixel data in a search area that is a part of the reference image and required to calculate a motion vector for the block; a motion vector operating unit (50) calculating the motion vector by repeatedly (i) reading out, from the second memory unit (30), the pixel data and (ii) performing a predetermined operation on the pixel data; and a decoding unit (60) decoding the block using the calculated motion vector.
摘要翻译：解码装置（100）包括：第一存储单元，存储解码中要参考的解码参考图像的像素数据; 具有比第一存储单元（20）的存储容量小的存储容量的第二存储器单元（30），并且提供比由第一存储器单元（20）提供的数据读取速度更快的数据读取速度; 搜索区域传送单元，从第一存储单元（20）向第二存储单元（30）传送作为参考图像的一部分的搜索区域中的像素数据，并且需要计算用于块; 运动矢量运算单元，通过重复地（i）从第二存储器单元（30）读出像素数据和（ii）对像素数据执行预定的操作来计算运动矢量; 以及解码单元（60），使用所计算的运动矢量对该块进行解码。

100. 发明申请

US20110135285A1 IMAGE CODING APPARATUS, METHOD, INTEGRATED CIRCUIT, AND PROGRAM 有权
标题翻译：图像编码设备，方法，集成电路和程序
公开(公告)号：US20110135285A1
公开(公告)日：2011-06-09
申请号：US13056762
申请日：2010-05-31
申请人： Takaaki Imanaka , Takashi Hashimoto
发明人： Takaaki Imanaka , Takashi Hashimoto
IPC分类号： H04N5/917 , H04N7/12
CPC分类号： H04N19/00678 , H04N19/44 , H04N19/51 , H04N19/52 , H04N19/57 , H04N19/583
摘要： An image coding apparatus (5x) includes: a search range control unit (5003a) which sets a search range (8013x) that requires a small amount of data to be transferred; an obtaining unit (5003b) which obtains data of pixels within the search range from an image memory (2002) storing the data; and a predicting unit (2015x) which performs motion estimation.
摘要翻译：图像编码装置（5x）包括：搜索范围控制部（5003a），其设定要传送少量数据的搜索范围（8013x）从存储数据的图像存储器（2002）获取搜索范围内的像素的数据的获取单元（5003b）和执行运动估计的预测单元（2015x）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式